Niles Salter Validark

Here is an overview of which ISA's support these instructions I compiled for an upcoming presentation:

BESM Soviet mainframes:
- BESM-6 (Designed in 1965. Produced 1968-1987) => AUX & APX
x86-64:
- BMI2 (Intel Haswell 2013+, AMD Excavator 2015+, Fast on AMD since Zen 3 2020+) => PDEP & PEXT
arm64 / aarch64:
SVE2 (optional, not required) => BDEP & BEXT & [BGRP](https://developer.arm.com/documentation/ddi0602/latest/SVE-Inst

	fn tbl4(
	table_part_1: @Vector(16, u8),
	table_part_2: @Vector(16, u8),
	table_part_3: @Vector(16, u8),
	table_part_4: @Vector(16, u8),
	indices: @Vector(8, u8)
	) @TypeOf(indices) {
	return struct {
	extern fn @"llvm.aarch64.neon.tbl4"(@TypeOf(table_part_1), @TypeOf(table_part_2), @TypeOf(table_part_3), @TypeOf(table_part_4), @TypeOf(indices)) @TypeOf(indices);
	}.@"llvm.aarch64.neon.tbl4"(table_part_1, table_part_2, table_part_3, table_part_4, indices);

	const std = @import("std");

	fn cmtst(a: anytype, comptime b: @TypeOf(a)) @TypeOf(a) {
	return @select(u8, (a & b) != @as(@TypeOf(a), @splat(0)), @as(@TypeOf(a), @splat(0xff)), @as(@TypeOf(a), @splat(0)));
	}

	fn unmovemask(x: u64) @Vector(64, u8) {
	const vec = @as(@Vector(8, u8), @bitCast(x));
	const interlaced_vec = std.simd.interlace(.{ vec, vec });

	export fn st4(vec: @Vector(64, u8), ptr: [*]u8) void {
	const chunks: [4]@Vector(16, u8) = @bitCast(vec);
	return struct {
	extern fn @"llvm.aarch64.neon.st4.v16i8.p0"(
	@Vector(16, u8),
	@Vector(16, u8),
	@Vector(16, u8),
	@Vector(16, u8),
	[*]u8
	) void;

	"use strict";

	// Adapted from
	// github.com/dashpay/dash/tree/develop/src/governance/common.cpp

	// USAGE
	// node ./gobject-hash-debugger.js

	var GObj = module.exports;

	/*
	Language: Zig
	Author: fwx <fwx5618177@gmail.com>
	*/

	export const zigLanguageSupport = (hljs) => {
	const LITERALS = ["true", "false", "null", "undefined"];
	const BUILT_INS = [
	"@This",
	"@import",

	export fn cls(e: u64) @TypeOf(e) {
	const e2: @TypeOf(e) = @bitCast(@as(std.meta.Int(.signed, @bitSizeOf(@TypeOf(e))), @bitCast(e)) >> (@bitSizeOf(@TypeOf(e)) - 1));
	return @clz(((e ^ e2) << 1) \| 1);
	}

	fn swarGe(x: anytype, y: @TypeOf(x)) @TypeOf(x) {
	const msb: @TypeOf(x) = @bitCast(@as(@Vector(@sizeOf(@TypeOf(x)), u8), @splat(0x80)));
	return (((x ^ y) & x) \| (~(x ^ y) & ((x \| msb) -% (y & ~msb))));
	}

	fn swarLe(x: anytype, y: @TypeOf(x)) @TypeOf(x) {
	return swarGe(y, x);
	}

	fn swarEq(x: anytype, y: @TypeOf(x)) @TypeOf(x) {

	const std = @import("std");

	export fn columnCountsVec(chunk: @Vector(16, u8)) @TypeOf(chunk) {
	var mask = chunk != @as(@TypeOf(chunk), @splat('\n'));
	var array_count = @select(u8, mask, @as(@TypeOf(chunk), @splat(1)), @as(@TypeOf(chunk), @splat(0)));

	inline for (0..std.math.log2(@sizeOf(@TypeOf(chunk)))) \|i\| {
	array_count = @select(u8, mask, array_count +% std.simd.shiftElementsRight(array_count, 1 << i, 0), array_count);
	mask = @select(bool, mask, std.simd.shiftElementsRight(mask, 1 << i, false), @as(@TypeOf(mask), @splat(false)));
	}

	const std = @import("std");
	const builtin = @import("builtin");

	const HAS_FAST_PDEP_AND_PEXT = blk: {
	const cpu_name = builtin.cpu.model.llvm_name orelse builtin.cpu.model.name;
	break :blk builtin.cpu.arch == .x86_64 and
	std.Target.x86.featureSetHas(builtin.cpu.features, .bmi2) and
	// pdep is microcoded (slow) on AMD architectures before Zen 3.
	!std.mem.startsWith(u8, cpu_name, "bdver") and
	(!std.mem.startsWith(u8, cpu_name, "znver") or cpu_name["znver".len] >= '3');