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@sprhawk
Last active October 12, 2020 15:33
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openocd for rk3368
source [find interface/jlink.cfg]
transport select swd
adapter speed 4000
reset_config none
gdb_target_description enable
source [find target/rk3368.cfg]
# reset_config trst_only
static int
swd_init(void) {
struct rk3368_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
struct rk3368_cru *cru = rockchip_get_cru();
rk_setreg(&grf->soc_con15, 1 << 13);
rk_clrsetreg(&grf->gpio2a_iomux, 1 << 14, 2 << 14);
rk_clrsetreg(&grf->gpio2b_iomux, 1, 2);
}
# scripts/target/rk3368.cfg
# Rockchip RK3368 Target
source [find target/swj-dp.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME rk3368
}
#
# Main DAP
#
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x5ba02477
}
# declare the one SWD tap to access the DAP
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID
# create the DAP
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -ignore-syspwrupack
set _TARGETNAME $_CHIPNAME.a53
set _CTINAME $_CHIPNAME.cti
set DBGBASE {0xffc30000 0xffc32000 0xffc34000 0xffc36000 0xffc50000 0xffc52000 0xffc54000 0xffc56000}
set CTIBASE {0xffc38000 0xffc39000 0xffc3a000 0xffc3b000 0xffc58000 0xffc59000 0xffc5a000 0xffc5b000}
set _cores 8
set _smp_command ""
for { set _core 0 } { $_core < $_cores } { incr _core } {
cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 0 \
-ctibase [lindex $CTIBASE $_core]
set _command "target create $_TARGETNAME.$_core aarch64 \
-dap $_CHIPNAME.dap -coreid $_core \
-dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core"
if { $_core != 0 } {
set _command "$_command -defer-examine"
set _smp_command "$_smp_command ${_TARGETNAME}.$_core"
} else {
set _smp_command "target smp ${_TARGETNAME}.$_core"
}
eval $_command
$_TARGETNAME.$_core configure -event reset-assert-post "aarch64 dbginit"
}
eval $_smp_command
cti create cti.sys -dap $_CHIPNAME.dap -ap-num 0 -ctibase 0xffc38000
targets $_TARGETNAME.0
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