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pdp7/star64 pcie

Created August 3, 2024 17:45
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star64 pcie
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star64 pcie
root
pine64
[ 0.000000] Linux version 5.15.131 (oe-user@oe-host) (riscv64-pine64-linux-gcc (GCC) 11.3.0, GNU ld (GNU Binutils) 2.38.20220708) #1 SMP Thu Sep 21 04:12:12 UTC 2023
[ 0.000000] Kernel command line: earlyprintk console=tty1 console=ttyS0,115200 rootwait splash quiet earlycon=sbi root=/dev/mmcblk1p4
[ 0.000000] Unknown kernel command line parameters "earlyprintk splash", will be passed to user space.
[ 0.910473] axp15060-regulator 5-0036: Register cpu_vdd done! vol range:500 ~ 1540 mV
[ 0.913472] pcie_plda 2c000000.pcie: Failed to get power-gpio, but maybe it's always on.
[ 0.913635] pcie_plda 2c000000.pcie: host bridge /soc/pcie@2C000000 ranges:
[ 0.913678] pcie_plda 2c000000.pcie: MEM 0x0038000000..0x003fffffff -> 0x0038000000
[ 0.913702] pcie_plda 2c000000.pcie: MEM 0x0980000000..0x09bfffffff -> 0x0980000000
[ 0.913747] ATR entry: 0x09c0000000 -> 0x0000000000 [0x0010000000] (param: 0x000001)
[ 0.913760] ATR entry: 0x0038000000 -> 0x0038000000 [0x0008000000] (param: 0x000000)
[ 0.913771] ATR entry: 0x0980000000 -> 0x0980000000 [0x0040000000] (param: 0x000000)
[ 1.240515] pcie_plda 2c000000.pcie: Port link up.
[ 1.240675] pcie_plda 2c000000.pcie: PCI host bridge to bus 0000:00
[ 1.240687] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 1.240700] pci_bus 0000:00: root bus resource [mem 0x38000000-0x3fffffff]
[ 1.240713] pci_bus 0000:00: root bus resource [mem 0x980000000-0x9bfffffff pref]
[ 1.240750] pci 0000:00:00.0: [1556:1111] type 01 class 0x060400
[ 1.240772] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0xffffffff 64bit pref]
[ 1.240830] pci 0000:00:00.0: supports D1 D2
[ 1.240840] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[ 1.244605] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 1.244761] pci 0000:01:00.0: [1415:c140] type 00 class 0x070002
[ 1.244794] pci 0000:01:00.0: reg 0x10: [io 0x0000-0x0007]
[ 1.244937] pci 0000:01:00.0: supports D1 D2
[ 1.244946] pci 0000:01:00.0: PME# supported from D1 D2 D3hot D3cold
[ 1.245176] pci 0000:01:00.1: [1415:c141] type 00 class 0x070002
[ 1.245209] pci 0000:01:00.1: reg 0x10: [io 0x0000-0x0007]
[ 1.245344] pci 0000:01:00.1: supports D1 D2
[ 1.245353] pci 0000:01:00.1: PME# supported from D1 D2 D3hot D3cold
[ 1.248957] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
[ 1.248991] pci 0000:00:00.0: BAR 0: no space for [mem size 0x100000000 64bit pref]
[ 1.249005] pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x100000000 64bit pref]
[ 1.249020] pci 0000:01:00.0: BAR 0: no space for [io size 0x0008]
[ 1.249031] pci 0000:01:00.0: BAR 0: failed to assign [io size 0x0008]
[ 1.249042] pci 0000:01:00.1: BAR 0: no space for [io size 0x0008]
[ 1.249053] pci 0000:01:00.1: BAR 0: failed to assign [io size 0x0008]
[ 1.249065] pci 0000:00:00.0: PCI bridge to [bus 01]
[ 1.249309] serial: probe of 0000:01:00.0 failed with error -12
[ 1.249476] serial: probe of 0000:01:00.1 failed with error -12
root@star64:~# lspci
00:00.0 PCI bridge: PLDA XpressRich-AXI Ref Design (rev 02)
01:00.0 Serial controller: Oxford Semiconductor Ltd OXPCIe952 Legacy 950 UART
01:00.1 Serial controller: Oxford Semiconductor Ltd OXPCIe952 Legacy 950 UART
root@star64:~#
root@star64:~# lspci -v
00:00.0 PCI bridge: PLDA XpressRich-AXI Ref Design (rev 02) (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0
Memory at <unassigned> (64-bit, prefetchable) [disabled]
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: 00000000-00000fff [size=4K]
Memory behind bridge: [disabled]
Prefetchable memory behind bridge: 0000000000000000-00000000000fffff [size=1M]
Capabilities: [80] Express Root Port (Slot+), MSI 00
Capabilities: [e0] MSI: Enable- Count=1/32 Maskable+ 64bit+
Capabilities: [f8] Power Management version 3
Capabilities: [100] Vendor Specific Information: ID=1556 Rev=1 Len=008 <?>
Capabilities: [200] Advanced Error Reporting
01:00.0 Serial controller: Oxford Semiconductor Ltd OXPCIe952 Legacy 950 UART (prog-if 02 [16550])
Subsystem: Oxford Semiconductor Ltd OXPCIe952 Legacy 950 UART
Flags: fast devsel, IRQ 53
I/O ports at <unassigned> [disabled]
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
Capabilities: [70] Express Legacy Endpoint, MSI 00
Capabilities: [100] Device Serial Number 00-30-e0-11-11-00-01-40
Capabilities: [110] Power Budgeting <?>
01:00.1 Serial controller: Oxford Semiconductor Ltd OXPCIe952 Legacy 950 UART (prog-if 02 [16550])
Subsystem: Oxford Semiconductor Ltd OXPCIe952 Legacy 950 UART
Flags: fast devsel, IRQ 54
I/O ports at <unassigned> [disabled]
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
Capabilities: [70] Express Legacy Endpoint, MSI 00
Capabilities: [100] Power Budgeting <?>
root@star64:~# lspci -v
00:00.0 PCI bridge: PLDA XpressRich-AXI Ref Design (rev 02) (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0
Memory at <unassigned> (64-bit, prefetchable) [disabled]
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: 00000000-00000fff [size=4K]
Memory behind bridge: [disabled]
Prefetchable memory behind bridge: 0000000000000000-00000000000fffff [size=1M]
Capabilities: [80] Express Root Port (Slot+), MSI 00
Capabilities: [e0] MSI: Enable- Count=1/32 Maskable+ 64bit+
Capabilities: [f8] Power Management version 3
Capabilities: [100] Vendor Specific Information: ID=1556 Rev=1 Len=008 <?>
Capabilities: [200] Advanced Error Reporting
01:00.0 Serial controller: Oxford Semiconductor Ltd OXPCIe952 Legacy 950 UART (prog-if 02 [16550])
Subsystem: Oxford Semiconductor Ltd OXPCIe952 Legacy 950 UART
Flags: fast devsel, IRQ 53
I/O ports at <unassigned> [disabled]
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
Capabilities: [70] Express Legacy Endpoint, MSI 00
Capabilities: [100] Device Serial Number 00-30-e0-11-11-00-01-40
Capabilities: [110] Power Budgeting <?>
01:00.1 Serial controller: Oxford Semiconductor Ltd OXPCIe952 Legacy 950 UART (prog-if 02 [16550])
Subsystem: Oxford Semiconductor Ltd OXPCIe952 Legacy 950 UART
Flags: fast devsel, IRQ 54
I/O ports at <unassigned> [disabled]
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
Capabilities: [70] Express Legacy Endpoint, MSI 00
Capabilities: [100] Power Budgeting <?>
root@star64:~# ^C
root@star64:~# lspci -vvv
00:00.0 PCI bridge: PLDA XpressRich-AXI Ref Design (rev 02) (prog-if 00 [Normal decode])
Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
Interrupt: pin A routed to IRQ 0
Region 0: Memory at <unassigned> (64-bit, prefetchable) [disabled]
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: 00000000-00000fff [size=4K]
Memory behind bridge: fff00000-000fffff [disabled]
Prefetchable memory behind bridge: 0000000000000000-00000000000fffff [size=1M]
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [80] Express (v2) Root Port (Slot+), MSI 00
DevCap: MaxPayload 128 bytes, PhantFunc 0
ExtTag+ RBE+
DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq-
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
LnkCap: Port #1, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <64ns, L1 <1us
ClockPM- Surprise- LLActRep- BwNot+ ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s (downgraded), Width x1 (ok)
TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
Slot #0, PowerLimit 0.000W; Interlock- NoCompl-
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock-
Changed: MRL- PresDet- LinkState-
RootCap: CRSVisible-
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ NROPrPrP- LTR+
10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt+ EETLPPrefix-
EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
FRS- LN System CLS Not Supported, TPHComp- ExtTPHComp- ARIFwd-
AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR- OBFF Disabled, ARIFwd-
AtomicOpsCtl: ReqEn- EgressBlck-
LnkCap2: Supported Link Speeds: 2.5-5GT/s, Crosslink- Retimer- 2Retimers- DRS-
LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance De-emphasis: -6dB
LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete- EqualizationPhase1-
EqualizationPhase2- EqualizationPhase3- LinkEqualizationRequest-
Retimer- 2Retimers- CrosslinkRes: unsupported
Capabilities: [e0] MSI: Enable- Count=1/32 Maskable+ 64bit+
Address: 0000000000000000 Data: 0000
Masking: 00000000 Pending: 00000000
Capabilities: [f8] Power Management version 3
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [100 v1] Vendor Specific Information: ID=1556 Rev=1 Len=008 <?>
Capabilities: [200 v2] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap+ ECRCChkEn-
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
HeaderLog: 00000000 00000000 00000000 00000000
RootCmd: CERptEn- NFERptEn- FERptEn-
RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd-
FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0
ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000
01:00.0 Serial controller: Oxford Semiconductor Ltd OXPCIe952 Legacy 950 UART (prog-if 02 [16550])
Subsystem: Oxford Semiconductor Ltd OXPCIe952 Legacy 950 UART
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Interrupt: pin A routed to IRQ 53
Region 0: I/O ports at <unassigned> [disabled]
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=55mA PME(D0-,D1+,D2+,D3hot+,D3cold+)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
Address: 0000000000000000 Data: 0000
Capabilities: [70] Express (v1) Legacy Endpoint, MSI 00
DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <128ns, L1 <2us
ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend-
LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <512ns, L1 <64us
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp-
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s (ok), Width x1 (ok)
TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
Capabilities: [100 v1] Device Serial Number 00-30-e0-11-11-00-01-40
Capabilities: [110 v1] Power Budgeting <?>
01:00.1 Serial controller: Oxford Semiconductor Ltd OXPCIe952 Legacy 950 UART (prog-if 02 [16550])
Subsystem: Oxford Semiconductor Ltd OXPCIe952 Legacy 950 UART
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Interrupt: pin B routed to IRQ 54
Region 0: I/O ports at <unassigned> [disabled]
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=55mA PME(D0-,D1+,D2+,D3hot+,D3cold+)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
Address: 0000000000000000 Data: 0000
Capabilities: [70] Express (v1) Legacy Endpoint, MSI 00
DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <128ns, L1 <2us
ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend-
LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <512ns, L1 <64us
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp-
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s (ok), Width x1 (ok)
TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
Capabilities: [100 v1] Power Budgeting <?>
root@star64:~# cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
1: 18 0 0 0 SiFive PLIC 69 Edge timer@13050000.ch0
2: 18 0 0 0 SiFive PLIC 70 Edge timer@13050000.ch1
3: 18 0 0 0 SiFive PLIC 71 Edge timer@13050000.ch2
4: 18 0 0 0 SiFive PLIC 72 Edge timer@13050000.ch3
5: 54051 22810 38571 9583 RISC-V INTC 5 Edge riscv-timer
6: 0 0 0 0 SiFive PLIC 1 Edge l2_ecc
7: 1 0 0 0 SiFive PLIC 3 Edge l2_ecc
8: 1 0 0 0 SiFive PLIC 4 Edge l2_ecc
10: 0 0 0 0 SiFive PLIC 2 Edge l2_ecc
11: 0 0 0 0 SiFive PLIC 25 Edge 13010000.spi
12: 0 0 0 0 SiFive PLIC 68 Edge 13070000.wdog
15: 0 0 0 0 SiFive PLIC 12 Edge rtc_starfive
16: 5344 0 0 0 SiFive PLIC 111 Edge 17030000.power-controller
17: 4134 0 0 0 SiFive PLIC 32 Edge ttyS0
18: 0 0 0 0 SiFive PLIC 73 Edge dw_axi_dmac_platform
21: 222 0 0 0 SiFive PLIC 81 Edge 120e0000.tmon
22: 3 0 0 0 SiFive PLIC 30 Edge 1600c000.trng
23: 0 0 0 0 SiFive PLIC 29 Edge pl08xdmac
24: 22 0 0 0 SiFive PLIC 28 Edge 16000000.crypto
25: 0 0 0 0 SiFive PLIC 35 Edge 10030000.i2c
26: 37 0 0 0 SiFive PLIC 37 Edge 10050000.i2c
27: 64032 0 0 0 SiFive PLIC 50 Edge 12050000.i2c
28: 0 0 0 0 SiFive PLIC 51 Edge 12060000.i2c
29: 103 0 0 0 SiFive PLIC 74 Edge dw-mci
30: 11984 0 0 0 SiFive PLIC 75 Edge dw-mci
31: 0 0 0 0 SiFive PLIC 92 Edge vin_axiwr_irq
32: 0 0 0 0 SiFive PLIC 87 Edge vin_isp_irq
35: 0 0 0 0 SiFive PLIC 90 Edge vin_isp_irq_csiline
36: 0 0 0 0 SiFive PLIC 14 Edge JPU_CODEC_IRQ
37: 0 0 0 0 SiFive PLIC 13 Edge vpu_irq
38: 0 0 0 0 SiFive PLIC 15 Edge VPU_CODEC_IRQ
39: 0 0 0 0 SiFive PLIC 7 Edge eth0
40: 0 0 0 0 SiFive PLIC 6 Edge eth0
41: 0 0 0 0 SiFive PLIC 5 Edge eth0
42: 0 0 0 0 SiFive PLIC 78 Edge eth1
43: 0 0 0 0 SiFive PLIC 77 Edge eth1
44: 0 0 0 0 SiFive PLIC 76 Edge eth1
45: 0 0 0 0 SiFive PLIC 82 Edge pvrsrvkm
46: 0 0 0 0 SiFive PLIC 38 Edge pl022
48: 0 0 0 0 SiFive PLIC 26 Edge hifi4_core
50: 0 0 0 0 SiFive PLIC 95 Edge 29400000.dc8200
51: 1 0 0 0 SiFive PLIC 98 Edge 295d0000.mipi
52: 0 0 0 0 SiFive PLIC 99 Edge 29590000.hdmi
55: 1931184 0 0 0 SiFive PLIC 100 Edge xhci-hcd:usb1
57: 0 0 0 0 SiFive PLIC 110 Edge 10100000.usb
58: 0 0 0 0 13040000.gpio 15 Edge hdmi
IPI0: 63 92 115 203 Rescheduling interrupts
IPI1: 5806 247551 493286 121815 Function call interrupts
IPI2: 0 0 0 0 CPU stop interrupts
IPI3: 33442 8624 13643 3633 IRQ work interrupts
IPI4: 0 0 0 0 Timer broadcast interrupts
root@star64:~#
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