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merryhime/signatures.cpp

Created January 15, 2018 21:09
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signatures.cpp
void ADR(Imm<2> immlo, Imm<19> immhi, Reg Rd);
void ADRP(Imm<2> immlo, Imm<19> immhi, Reg Rd);
void ADD_addsub_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd);
void ADDS_addsub_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd);
void SUB_addsub_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd);
void SUBS_addsub_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd);
void AND_log_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd);
void ORR_log_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd);
void EOR_log_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd);
void ANDS_log_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd);
void MOVN(bool sf, Imm<2> hw, Imm<16> imm16, Reg Rd);
void MOVZ(bool sf, Imm<2> hw, Imm<16> imm16, Reg Rd);
void MOVK(bool sf, Imm<2> hw, Imm<16> imm16, Reg Rd);
void SBFM(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd);
void BFM(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd);
void UBFM(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd);
void EXTR(bool sf, bool N, Reg Rm, Imm<6> imms, Reg Rn, Reg Rd);
void B_cond(Imm<19> imm19, Cond cond);
void SVC(Imm<16> imm16);
void HVC(Imm<16> imm16);
void SMC(Imm<16> imm16);
void BRK(Imm<16> imm16);
void HLT(Imm<16> imm16);
void DCPS1(Imm<16> imm16);
void DCPS2(Imm<16> imm16);
void DCPS3(Imm<16> imm16);
void MSR_imm(Imm<3> op1, Imm<4> CRm, Imm<3> op2);
void HINT(Imm<4> CRm, Imm<3> op2);
void NOP();
void YIELD();
void WFE();
void WFI();
void SEV();
void SEVL();
void XPAC_1(bool D, Reg Rd);
void XPAC_2();
void PACIA_1(bool Z, Reg Rn, Reg Rd);
void PACIA_2();
void PACIB_1(bool Z, Reg Rn, Reg Rd);
void PACIB_2();
void AUTIA_1(bool Z, Reg Rn, Reg Rd);
void AUTIA_2();
void AUTIB_1(bool Z, Reg Rn, Reg Rd);
void AUTIB_2();
void ESB();
void PSB();
void CLREX(Imm<4> CRm);
void DSB(Imm<4> CRm);
void DMB(Imm<4> CRm);
void ISB(Imm<4> CRm);
void SYS(Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt);
void MSR_reg(bool o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt);
void SYSL(Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt);
void MRS(bool o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt);
void BR(Reg Rn);
void BRA(bool Z, bool M, Reg Rn, Reg Rm);
void BLR(Reg Rn);
void BLRA(bool Z, bool M, Reg Rn, Reg Rm);
void RET(Reg Rn);
void RETA(bool M);
void ERET();
void ERETA(bool M);
void DRPS();
void B_uncond(Imm<26> imm26);
void BL(Imm<26> imm26);
void CBZ(bool sf, Imm<19> imm19, Reg Rt);
void CBNZ(bool sf, Imm<19> imm19, Reg Rt);
void TBZ(Imm<1> b5, Imm<5> b40, Imm<14> imm14, Reg Rt);
void TBNZ(Imm<1> b5, Imm<5> b40, Imm<14> imm14, Reg Rt);
void ST4_advsimd_mult_1(bool Q, Imm<2> size, Reg Rn, Reg Rt);
void ST4_advsimd_mult_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Reg Rt);
void ST1_advsimd_mult_1(bool Q, Imm<2> size, Reg Rn, Reg Rt);
void ST1_advsimd_mult_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Reg Rt);
void ST3_advsimd_mult_1(bool Q, Imm<2> size, Reg Rn, Reg Rt);
void ST3_advsimd_mult_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Reg Rt);
void ST2_advsimd_mult_1(bool Q, Imm<2> size, Reg Rn, Reg Rt);
void ST2_advsimd_mult_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Reg Rt);
void LD4_advsimd_mult_1(bool Q, Imm<2> size, Reg Rn, Reg Rt);
void LD4_advsimd_mult_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Reg Rt);
void LD1_advsimd_mult_1(bool Q, Imm<2> size, Reg Rn, Reg Rt);
void LD1_advsimd_mult_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Reg Rt);
void LD3_advsimd_mult_1(bool Q, Imm<2> size, Reg Rn, Reg Rt);
void LD3_advsimd_mult_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Reg Rt);
void LD2_advsimd_mult_1(bool Q, Imm<2> size, Reg Rn, Reg Rt);
void LD2_advsimd_mult_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Reg Rt);
void ST1_advsimd_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
void ST1_advsimd_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt);
void ST3_advsimd_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
void ST3_advsimd_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt);
void ST2_advsimd_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
void ST2_advsimd_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt);
void ST4_advsimd_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
void ST4_advsimd_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt);
void LD1_advsimd_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
void LD1_advsimd_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt);
void LD3_advsimd_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
void LD3_advsimd_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt);
void LD1R_advsimd_1(bool Q, Imm<2> size, Reg Rn, Vec Vt);
void LD1R_advsimd_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt);
void LD3R_advsimd_1(bool Q, Imm<2> size, Reg Rn, Vec Vt);
void LD3R_advsimd_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt);
void LD2_advsimd_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
void LD2_advsimd_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt);
void LD4_advsimd_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
void LD4_advsimd_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt);
void LD2R_advsimd_1(bool Q, Imm<2> size, Reg Rn, Vec Vt);
void LD2R_advsimd_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt);
void LD4R_advsimd_1(bool Q, Imm<2> size, Reg Rn, Vec Vt);
void LD4R_advsimd_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt);
void STXRB(Reg Rs, Reg Rn, Reg Rt);
void STLXRB(Reg Rs, Reg Rn, Reg Rt);
void CASP(bool sz, bool L, Reg Rs, bool o0, Reg Rn, Reg Rt);
void LDXRB(Reg Rn, Reg Rt);
void LDAXRB(Reg Rn, Reg Rt);
void STLLRB(Reg Rn, Reg Rt);
void STLRB(Reg Rn, Reg Rt);
void CASB(bool L, Reg Rs, bool o0, Reg Rn, Reg Rt);
void LDLARB(Reg Rn, Reg Rt);
void LDARB(Reg Rn, Reg Rt);
void STXRH(Reg Rs, Reg Rn, Reg Rt);
void STLXRH(Reg Rs, Reg Rn, Reg Rt);
void LDXRH(Reg Rn, Reg Rt);
void LDAXRH(Reg Rn, Reg Rt);
void STLLRH(Reg Rn, Reg Rt);
void STLRH(Reg Rn, Reg Rt);
void CASH(bool L, Reg Rs, bool o0, Reg Rn, Reg Rt);
void LDLARH(Reg Rn, Reg Rt);
void LDARH(Reg Rn, Reg Rt);
void STXR(Reg Rs, Reg Rn, Reg Rt);
void STLXR(Reg Rs, Reg Rn, Reg Rt);
void STXP(bool sz, Reg Rs, Reg Rt2, Reg Rn, Reg Rt);
void STLXP(bool sz, Reg Rs, Reg Rt2, Reg Rn, Reg Rt);
void LDXR(Reg Rn, Reg Rt);
void LDAXR(Reg Rn, Reg Rt);
void LDXP(bool sz, Reg Rt2, Reg Rn, Reg Rt);
void LDAXP(bool sz, Reg Rt2, Reg Rn, Reg Rt);
void STLLR(Reg Rn, Reg Rt);
void STLR(Reg Rn, Reg Rt);
void CAS(bool L, Reg Rs, bool o0, Reg Rn, Reg Rt);
void LDLAR(Reg Rn, Reg Rt);
void LDAR(Reg Rn, Reg Rt);
void LDR_lit_gen(Imm<19> imm19, Reg Rt);
void LDR_lit_fpsimd(Imm<2> opc, Imm<19> imm19, Vec Vt);
void LDRSW_lit(Imm<19> imm19, Reg Rt);
void PRFM_lit(Imm<19> imm19, Reg Rt);
void STNP_gen(Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt);
void LDNP_gen(Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt);
void STNP_fpsimd(Imm<2> opc, Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt);
void LDNP_fpsimd(Imm<2> opc, Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt);
void STP_gen_1(Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt);
void STP_gen_2(Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt);
void STP_gen_3(Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt);
void LDP_gen_1(Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt);
void LDP_gen_2(Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt);
void LDP_gen_3(Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt);
void STP_fpsimd_1(Imm<2> opc, Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt);
void STP_fpsimd_2(Imm<2> opc, Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt);
void STP_fpsimd_3(Imm<2> opc, Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt);
void LDP_fpsimd_1(Imm<2> opc, Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt);
void LDP_fpsimd_2(Imm<2> opc, Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt);
void LDP_fpsimd_3(Imm<2> opc, Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt);
void LDPSW_1(Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt);
void LDPSW_2(Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt);
void LDPSW_3(Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt);
void STURB(Imm<9> imm9, Reg Rn, Reg Rt);
void LDURB(Imm<9> imm9, Reg Rn, Reg Rt);
void LDURSB(Imm<9> imm9, Reg Rn, Reg Rt);
void STUR_fpsimd(Imm<2> size, Imm<9> imm9, Reg Rn, Vec Vt);
void LDUR_fpsimd(Imm<2> size, Imm<9> imm9, Reg Rn, Vec Vt);
void STURH(Imm<9> imm9, Reg Rn, Reg Rt);
void LDURH(Imm<9> imm9, Reg Rn, Reg Rt);
void LDURSH(Imm<9> imm9, Reg Rn, Reg Rt);
void STUR_gen(Imm<9> imm9, Reg Rn, Reg Rt);
void LDUR_gen(Imm<9> imm9, Reg Rn, Reg Rt);
void LDURSW(Imm<9> imm9, Reg Rn, Reg Rt);
void PRFUM(Imm<9> imm9, Reg Rn, Reg Rt);
void STRB_imm_1(Imm<9> imm9, Reg Rn, Reg Rt);
void STRB_imm_2(Imm<9> imm9, Reg Rn, Reg Rt);
void STRB_imm_3(Imm<12> imm12, Reg Rn, Reg Rt);
void LDRB_imm_1(Imm<9> imm9, Reg Rn, Reg Rt);
void LDRB_imm_2(Imm<9> imm9, Reg Rn, Reg Rt);
void LDRB_imm_3(Imm<12> imm12, Reg Rn, Reg Rt);
void LDRSB_imm_1(Imm<9> imm9, Reg Rn, Reg Rt);
void LDRSB_imm_2(Imm<9> imm9, Reg Rn, Reg Rt);
void LDRSB_imm_3(Imm<12> imm12, Reg Rn, Reg Rt);
void STR_imm_fpsimd_1(Imm<2> size, Imm<9> imm9, Reg Rn, Vec Vt);
void STR_imm_fpsimd_2(Imm<2> size, Imm<9> imm9, Reg Rn, Vec Vt);
void STR_imm_fpsimd_3(Imm<2> size, Imm<12> imm12, Reg Rn, Vec Vt);
void LDR_imm_fpsimd_1(Imm<2> size, Imm<9> imm9, Reg Rn, Vec Vt);
void LDR_imm_fpsimd_2(Imm<2> size, Imm<9> imm9, Reg Rn, Vec Vt);
void LDR_imm_fpsimd_3(Imm<2> size, Imm<12> imm12, Reg Rn, Vec Vt);
void STRH_imm_1(Imm<9> imm9, Reg Rn, Reg Rt);
void STRH_imm_2(Imm<9> imm9, Reg Rn, Reg Rt);
void STRH_imm_3(Imm<12> imm12, Reg Rn, Reg Rt);
void LDRH_imm_1(Imm<9> imm9, Reg Rn, Reg Rt);
void LDRH_imm_2(Imm<9> imm9, Reg Rn, Reg Rt);
void LDRH_imm_3(Imm<12> imm12, Reg Rn, Reg Rt);
void LDRSH_imm_1(Imm<9> imm9, Reg Rn, Reg Rt);
void LDRSH_imm_2(Imm<9> imm9, Reg Rn, Reg Rt);
void LDRSH_imm_3(Imm<12> imm12, Reg Rn, Reg Rt);
void STR_imm_gen_1(Imm<9> imm9, Reg Rn, Reg Rt);
void STR_imm_gen_2(Imm<9> imm9, Reg Rn, Reg Rt);
void STR_imm_gen_3(Imm<12> imm12, Reg Rn, Reg Rt);
void LDR_imm_gen_1(Imm<9> imm9, Reg Rn, Reg Rt);
void LDR_imm_gen_2(Imm<9> imm9, Reg Rn, Reg Rt);
void LDR_imm_gen_3(Imm<12> imm12, Reg Rn, Reg Rt);
void LDRSW_imm_1(Imm<9> imm9, Reg Rn, Reg Rt);
void LDRSW_imm_2(Imm<9> imm9, Reg Rn, Reg Rt);
void LDRSW_imm_3(Imm<12> imm12, Reg Rn, Reg Rt);
void STTRB(Imm<9> imm9, Reg Rn, Reg Rt);
void LDTRB(Imm<9> imm9, Reg Rn, Reg Rt);
void LDTRSB(Imm<9> imm9, Reg Rn, Reg Rt);
void STTRH(Imm<9> imm9, Reg Rn, Reg Rt);
void LDTRH(Imm<9> imm9, Reg Rn, Reg Rt);
void LDTRSH(Imm<9> imm9, Reg Rn, Reg Rt);
void STTR(Imm<9> imm9, Reg Rn, Reg Rt);
void LDTR(Imm<9> imm9, Reg Rn, Reg Rt);
void LDTRSW(Imm<9> imm9, Reg Rn, Reg Rt);
void LDADDB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void LDCLRB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void LDEORB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void LDSETB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void LDSMAXB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void LDSMINB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void LDUMAXB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void LDUMINB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void SWPB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void LDAPRB(Reg Rn, Reg Rt);
void LDADDH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void LDCLRH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void LDEORH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void LDSETH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void LDSMAXH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void LDSMINH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void LDUMAXH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void LDUMINH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void SWPH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void LDAPRH(Reg Rn, Reg Rt);
void LDADD(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void LDCLR(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void LDEOR(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void LDSET(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void LDSMAX(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void LDSMIN(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void LDUMAX(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void LDUMIN(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void SWP(bool A, bool R, Reg Rs, Reg Rn, Reg Rt);
void LDAPR(Reg Rn, Reg Rt);
void STRB_reg(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt);
void LDRB_reg(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt);
void LDRSB_reg(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt);
void STR_reg_fpsimd(Imm<2> size, Reg Rm, Imm<3> option, bool S, Reg Rn, Vec Vt);
void LDR_reg_fpsimd(Imm<2> size, Reg Rm, Imm<3> option, bool S, Reg Rn, Vec Vt);
void STRH_reg(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt);
void LDRH_reg(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt);
void LDRSH_reg(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt);
void STR_reg_gen(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt);
void LDR_reg_gen(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt);
void LDRSW_reg(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt);
void PRFM_reg(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt);
void LDRA(bool M, bool S, Imm<9> imm9, bool W, Reg Rn, Reg Rt);
void PRFM_imm(Imm<12> imm12, Reg Rn, Reg Rt);
void UDIV(bool sf, Reg Rm, Reg Rn, Reg Rd);
void SDIV(bool sf, Reg Rm, Reg Rn, Reg Rd);
void LSLV(bool sf, Reg Rm, Reg Rn, Reg Rd);
void LSRV(bool sf, Reg Rm, Reg Rn, Reg Rd);
void ASRV(bool sf, Reg Rm, Reg Rn, Reg Rd);
void RORV(bool sf, Reg Rm, Reg Rn, Reg Rd);
void CRC32(bool sf, Reg Rm, Imm<2> sz, Reg Rn, Reg Rd);
void CRC32C(bool sf, Reg Rm, Imm<2> sz, Reg Rn, Reg Rd);
void PACGA(Reg Rm, Reg Rn, Reg Rd);
void RBIT_int(bool sf, Reg Rn, Reg Rd);
void REV16_int(bool sf, Reg Rn, Reg Rd);
void REV(bool sf, Reg Rn, Reg Rd);
void CLZ_int(bool sf, Reg Rn, Reg Rd);
void CLS_int(bool sf, Reg Rn, Reg Rd);
void REV32_int(Reg Rn, Reg Rd);
void PACDA(bool Z, Reg Rn, Reg Rd);
void PACDB(bool Z, Reg Rn, Reg Rd);
void AUTDA(bool Z, Reg Rn, Reg Rd);
void AUTDB(bool Z, Reg Rn, Reg Rd);
void AND_log_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd);
void BIC_log_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd);
void ORR_log_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd);
void ORN_log_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd);
void EOR_log_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd);
void EON(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd);
void ANDS_log_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd);
void BICS(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd);
void ADD_addsub_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd);
void ADDS_addsub_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd);
void SUB_addsub_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd);
void SUBS_addsub_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd);
void ADD_addsub_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg Rn, Reg Rd);
void ADDS_addsub_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg Rn, Reg Rd);
void SUB_addsub_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg Rn, Reg Rd);
void SUBS_addsub_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg Rn, Reg Rd);
void ADC(bool sf, Reg Rm, Reg Rn, Reg Rd);
void ADCS(bool sf, Reg Rm, Reg Rn, Reg Rd);
void SBC(bool sf, Reg Rm, Reg Rn, Reg Rd);
void SBCS(bool sf, Reg Rm, Reg Rn, Reg Rd);
void CCMN_reg(bool sf, Reg Rm, Cond cond, Reg Rn, Imm<4> nzcv);
void CCMP_reg(bool sf, Reg Rm, Cond cond, Reg Rn, Imm<4> nzcv);
void CCMN_imm(bool sf, Imm<5> imm5, Cond cond, Reg Rn, Imm<4> nzcv);
void CCMP_imm(bool sf, Imm<5> imm5, Cond cond, Reg Rn, Imm<4> nzcv);
void CSEL(bool sf, Reg Rm, Cond cond, Reg Rn, Reg Rd);
void CSINC(bool sf, Reg Rm, Cond cond, Reg Rn, Reg Rd);
void CSINV(bool sf, Reg Rm, Cond cond, Reg Rn, Reg Rd);
void CSNEG(bool sf, Reg Rm, Cond cond, Reg Rn, Reg Rd);
void MADD(bool sf, Reg Rm, Reg Ra, Reg Rn, Reg Rd);
void MSUB(bool sf, Reg Rm, Reg Ra, Reg Rn, Reg Rd);
void SMADDL(Reg Rm, Reg Ra, Reg Rn, Reg Rd);
void SMSUBL(Reg Rm, Reg Ra, Reg Rn, Reg Rd);
void SMULH(Reg Rm, Reg Rn, Reg Rd);
void UMADDL(Reg Rm, Reg Ra, Reg Rn, Reg Rd);
void UMSUBL(Reg Rm, Reg Ra, Reg Rn, Reg Rd);
void UMULH(Reg Rm, Reg Rn, Reg Rd);
void AESE_advsimd(Vec Vn, Vec Vd);
void AESD_advsimd(Vec Vn, Vec Vd);
void AESMC_advsimd(Vec Vn, Vec Vd);
void AESIMC_advsimd(Vec Vn, Vec Vd);
void SHA1C_advsimd(Vec Vm, Vec Vn, Vec Vd);
void SHA1P_advsimd(Vec Vm, Vec Vn, Vec Vd);
void SHA1M_advsimd(Vec Vm, Vec Vn, Vec Vd);
void SHA1SU0_advsimd(Vec Vm, Vec Vn, Vec Vd);
void SHA256H_advsimd(Vec Vm, Vec Vn, Vec Vd);
void SHA256H2_advsimd(Vec Vm, Vec Vn, Vec Vd);
void SHA256SU1_advsimd(Vec Vm, Vec Vn, Vec Vd);
void SHA1H_advsimd(Vec Vn, Vec Vd);
void SHA1SU1_advsimd(Vec Vn, Vec Vd);
void SHA256SU0_advsimd(Vec Vn, Vec Vd);
void DUP_advsimd_elt_1(Imm<5> imm5, Vec Vn, Vec Vd);
void DUP_advsimd_elt_2(bool Q, Imm<5> imm5, Vec Vn, Vec Vd);
void FMULX_advsimd_vec_1(Vec Vm, Vec Vn, Vec Vd);
void FMULX_advsimd_vec_2(bool sz, Vec Vm, Vec Vn, Vec Vd);
void FMULX_advsimd_vec_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FMULX_advsimd_vec_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
void FCMEQ_advsimd_reg_1(Vec Vm, Vec Vn, Vec Vd);
void FCMEQ_advsimd_reg_2(bool sz, Vec Vm, Vec Vn, Vec Vd);
void FCMEQ_advsimd_reg_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FCMEQ_advsimd_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
void FRECPS_advsimd_1(Vec Vm, Vec Vn, Vec Vd);
void FRECPS_advsimd_2(bool sz, Vec Vm, Vec Vn, Vec Vd);
void FRECPS_advsimd_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FRECPS_advsimd_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
void FRSQRTS_advsimd_1(Vec Vm, Vec Vn, Vec Vd);
void FRSQRTS_advsimd_2(bool sz, Vec Vm, Vec Vn, Vec Vd);
void FRSQRTS_advsimd_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FRSQRTS_advsimd_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
void FCMGE_advsimd_reg_1(Vec Vm, Vec Vn, Vec Vd);
void FCMGE_advsimd_reg_2(bool sz, Vec Vm, Vec Vn, Vec Vd);
void FCMGE_advsimd_reg_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FCMGE_advsimd_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
void FACGE_advsimd_1(Vec Vm, Vec Vn, Vec Vd);
void FACGE_advsimd_2(bool sz, Vec Vm, Vec Vn, Vec Vd);
void FACGE_advsimd_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FACGE_advsimd_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
void FABD_advsimd_1(Vec Vm, Vec Vn, Vec Vd);
void FABD_advsimd_2(bool sz, Vec Vm, Vec Vn, Vec Vd);
void FABD_advsimd_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FABD_advsimd_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
void FCMGT_advsimd_reg_1(Vec Vm, Vec Vn, Vec Vd);
void FCMGT_advsimd_reg_2(bool sz, Vec Vm, Vec Vn, Vec Vd);
void FCMGT_advsimd_reg_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FCMGT_advsimd_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
void FACGT_advsimd_1(Vec Vm, Vec Vn, Vec Vd);
void FACGT_advsimd_2(bool sz, Vec Vm, Vec Vn, Vec Vd);
void FACGT_advsimd_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FACGT_advsimd_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
void FCVTNS_advsimd_1(Vec Vn, Vec Vd);
void FCVTNS_advsimd_2(bool sz, Vec Vn, Vec Vd);
void FCVTNS_advsimd_3(bool Q, Vec Vn, Vec Vd);
void FCVTNS_advsimd_4(bool Q, bool sz, Vec Vn, Vec Vd);
void FCVTMS_advsimd_1(Vec Vn, Vec Vd);
void FCVTMS_advsimd_2(bool sz, Vec Vn, Vec Vd);
void FCVTMS_advsimd_3(bool Q, Vec Vn, Vec Vd);
void FCVTMS_advsimd_4(bool Q, bool sz, Vec Vn, Vec Vd);
void FCVTAS_advsimd_1(Vec Vn, Vec Vd);
void FCVTAS_advsimd_2(bool sz, Vec Vn, Vec Vd);
void FCVTAS_advsimd_3(bool Q, Vec Vn, Vec Vd);
void FCVTAS_advsimd_4(bool Q, bool sz, Vec Vn, Vec Vd);
void SCVTF_advsimd_int_1(Vec Vn, Vec Vd);
void SCVTF_advsimd_int_2(bool sz, Vec Vn, Vec Vd);
void SCVTF_advsimd_int_3(bool Q, Vec Vn, Vec Vd);
void SCVTF_advsimd_int_4(bool Q, bool sz, Vec Vn, Vec Vd);
void FCMGT_advsimd_zero_1(Vec Vn, Vec Vd);
void FCMGT_advsimd_zero_2(bool sz, Vec Vn, Vec Vd);
void FCMGT_advsimd_zero_3(bool Q, Vec Vn, Vec Vd);
void FCMGT_advsimd_zero_4(bool Q, bool sz, Vec Vn, Vec Vd);
void FCMEQ_advsimd_zero_1(Vec Vn, Vec Vd);
void FCMEQ_advsimd_zero_2(bool sz, Vec Vn, Vec Vd);
void FCMEQ_advsimd_zero_3(bool Q, Vec Vn, Vec Vd);
void FCMEQ_advsimd_zero_4(bool Q, bool sz, Vec Vn, Vec Vd);
void FCMLT_advsimd_1(Vec Vn, Vec Vd);
void FCMLT_advsimd_2(bool sz, Vec Vn, Vec Vd);
void FCMLT_advsimd_3(bool Q, Vec Vn, Vec Vd);
void FCMLT_advsimd_4(bool Q, bool sz, Vec Vn, Vec Vd);
void FCVTPS_advsimd_1(Vec Vn, Vec Vd);
void FCVTPS_advsimd_2(bool sz, Vec Vn, Vec Vd);
void FCVTPS_advsimd_3(bool Q, Vec Vn, Vec Vd);
void FCVTPS_advsimd_4(bool Q, bool sz, Vec Vn, Vec Vd);
void FCVTZS_advsimd_int_1(Vec Vn, Vec Vd);
void FCVTZS_advsimd_int_2(bool sz, Vec Vn, Vec Vd);
void FCVTZS_advsimd_int_3(bool Q, Vec Vn, Vec Vd);
void FCVTZS_advsimd_int_4(bool Q, bool sz, Vec Vn, Vec Vd);
void FRECPE_advsimd_1(Vec Vn, Vec Vd);
void FRECPE_advsimd_2(bool sz, Vec Vn, Vec Vd);
void FRECPE_advsimd_3(bool Q, Vec Vn, Vec Vd);
void FRECPE_advsimd_4(bool Q, bool sz, Vec Vn, Vec Vd);
void FRECPX_advsimd_1(Vec Vn, Vec Vd);
void FRECPX_advsimd_2(bool sz, Vec Vn, Vec Vd);
void FCVTNU_advsimd_1(Vec Vn, Vec Vd);
void FCVTNU_advsimd_2(bool sz, Vec Vn, Vec Vd);
void FCVTNU_advsimd_3(bool Q, Vec Vn, Vec Vd);
void FCVTNU_advsimd_4(bool Q, bool sz, Vec Vn, Vec Vd);
void FCVTMU_advsimd_1(Vec Vn, Vec Vd);
void FCVTMU_advsimd_2(bool sz, Vec Vn, Vec Vd);
void FCVTMU_advsimd_3(bool Q, Vec Vn, Vec Vd);
void FCVTMU_advsimd_4(bool Q, bool sz, Vec Vn, Vec Vd);
void FCVTAU_advsimd_1(Vec Vn, Vec Vd);
void FCVTAU_advsimd_2(bool sz, Vec Vn, Vec Vd);
void FCVTAU_advsimd_3(bool Q, Vec Vn, Vec Vd);
void FCVTAU_advsimd_4(bool Q, bool sz, Vec Vn, Vec Vd);
void UCVTF_advsimd_int_1(Vec Vn, Vec Vd);
void UCVTF_advsimd_int_2(bool sz, Vec Vn, Vec Vd);
void UCVTF_advsimd_int_3(bool Q, Vec Vn, Vec Vd);
void UCVTF_advsimd_int_4(bool Q, bool sz, Vec Vn, Vec Vd);
void FCMGE_advsimd_zero_1(Vec Vn, Vec Vd);
void FCMGE_advsimd_zero_2(bool sz, Vec Vn, Vec Vd);
void FCMGE_advsimd_zero_3(bool Q, Vec Vn, Vec Vd);
void FCMGE_advsimd_zero_4(bool Q, bool sz, Vec Vn, Vec Vd);
void FCMLE_advsimd_1(Vec Vn, Vec Vd);
void FCMLE_advsimd_2(bool sz, Vec Vn, Vec Vd);
void FCMLE_advsimd_3(bool Q, Vec Vn, Vec Vd);
void FCMLE_advsimd_4(bool Q, bool sz, Vec Vn, Vec Vd);
void FCVTPU_advsimd_1(Vec Vn, Vec Vd);
void FCVTPU_advsimd_2(bool sz, Vec Vn, Vec Vd);
void FCVTPU_advsimd_3(bool Q, Vec Vn, Vec Vd);
void FCVTPU_advsimd_4(bool Q, bool sz, Vec Vn, Vec Vd);
void FCVTZU_advsimd_int_1(Vec Vn, Vec Vd);
void FCVTZU_advsimd_int_2(bool sz, Vec Vn, Vec Vd);
void FCVTZU_advsimd_int_3(bool Q, Vec Vn, Vec Vd);
void FCVTZU_advsimd_int_4(bool Q, bool sz, Vec Vn, Vec Vd);
void FRSQRTE_advsimd_1(Vec Vn, Vec Vd);
void FRSQRTE_advsimd_2(bool sz, Vec Vn, Vec Vd);
void FRSQRTE_advsimd_3(bool Q, Vec Vn, Vec Vd);
void FRSQRTE_advsimd_4(bool Q, bool sz, Vec Vn, Vec Vd);
void SQRDMLAH_advsimd_vec_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SQRDMLAH_advsimd_vec_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SQRDMLSH_advsimd_vec_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SQRDMLSH_advsimd_vec_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SUQADD_advsimd_1(Imm<2> size, Vec Vn, Vec Vd);
void SUQADD_advsimd_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void SQABS_advsimd_1(Imm<2> size, Vec Vn, Vec Vd);
void SQABS_advsimd_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void CMGT_advsimd_zero_1(Imm<2> size, Vec Vn, Vec Vd);
void CMGT_advsimd_zero_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void CMEQ_advsimd_zero_1(Imm<2> size, Vec Vn, Vec Vd);
void CMEQ_advsimd_zero_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void CMLT_advsimd_1(Imm<2> size, Vec Vn, Vec Vd);
void CMLT_advsimd_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void ABS_advsimd_1(Imm<2> size, Vec Vn, Vec Vd);
void ABS_advsimd_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void SQXTN_advsimd_1(Imm<2> size, Vec Vn, Reg Rd);
void SQXTN_advsimd_2(bool Q, Imm<2> size, Vec Vn, Reg Rd);
void USQADD_advsimd_1(Imm<2> size, Vec Vn, Vec Vd);
void USQADD_advsimd_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void SQNEG_advsimd_1(Imm<2> size, Vec Vn, Vec Vd);
void SQNEG_advsimd_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void CMGE_advsimd_zero_1(Imm<2> size, Vec Vn, Vec Vd);
void CMGE_advsimd_zero_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void CMLE_advsimd_1(Imm<2> size, Vec Vn, Vec Vd);
void CMLE_advsimd_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void NEG_advsimd_1(Imm<2> size, Vec Vn, Vec Vd);
void NEG_advsimd_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void SQXTUN_advsimd_1(Imm<2> size, Vec Vn, Reg Rd);
void SQXTUN_advsimd_2(bool Q, Imm<2> size, Vec Vn, Reg Rd);
void UQXTN_advsimd_1(Imm<2> size, Vec Vn, Reg Rd);
void UQXTN_advsimd_2(bool Q, Imm<2> size, Vec Vn, Reg Rd);
void FCVTXN_advsimd_1(bool sz, Vec Vn, Reg Rd);
void FCVTXN_advsimd_2(bool Q, bool sz, Vec Vn, Reg Rd);
void ADDP_advsimd_pair(Imm<2> size, Vec Vn, Vec Vd);
void FMAXNMP_advsimd_pair_1(Vec Vn, Vec Vd);
void FMAXNMP_advsimd_pair_2(bool sz, Vec Vn, Vec Vd);
void FADDP_advsimd_pair_1(Vec Vn, Vec Vd);
void FADDP_advsimd_pair_2(bool sz, Vec Vn, Vec Vd);
void FMAXP_advsimd_pair_1(Vec Vn, Vec Vd);
void FMAXP_advsimd_pair_2(bool sz, Vec Vn, Vec Vd);
void FMINNMP_advsimd_pair_1(Vec Vn, Vec Vd);
void FMINNMP_advsimd_pair_2(bool sz, Vec Vn, Vec Vd);
void FMINP_advsimd_pair_1(Vec Vn, Vec Vd);
void FMINP_advsimd_pair_2(bool sz, Vec Vn, Vec Vd);
void SQDMLAL_advsimd_vec_1(Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
void SQDMLAL_advsimd_vec_2(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
void SQDMLSL_advsimd_vec_1(Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
void SQDMLSL_advsimd_vec_2(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
void SQDMULL_advsimd_vec_1(Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
void SQDMULL_advsimd_vec_2(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
void SQADD_advsimd_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SQADD_advsimd_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SQSUB_advsimd_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SQSUB_advsimd_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void CMGT_advsimd_reg_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void CMGT_advsimd_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void CMGE_advsimd_reg_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void CMGE_advsimd_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SSHL_advsimd_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SSHL_advsimd_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SQSHL_advsimd_reg_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SQSHL_advsimd_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SRSHL_advsimd_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SRSHL_advsimd_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SQRSHL_advsimd_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SQRSHL_advsimd_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void ADD_advsimd_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void ADD_advsimd_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void CMTST_advsimd_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void CMTST_advsimd_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SQDMULH_advsimd_vec_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SQDMULH_advsimd_vec_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void UQADD_advsimd_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void UQADD_advsimd_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void UQSUB_advsimd_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void UQSUB_advsimd_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void CMHI_advsimd_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void CMHI_advsimd_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void CMHS_advsimd_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void CMHS_advsimd_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void USHL_advsimd_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void USHL_advsimd_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void UQSHL_advsimd_reg_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void UQSHL_advsimd_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void URSHL_advsimd_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void URSHL_advsimd_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void UQRSHL_advsimd_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void UQRSHL_advsimd_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SUB_advsimd_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SUB_advsimd_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void CMEQ_advsimd_reg_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void CMEQ_advsimd_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SQRDMULH_advsimd_vec_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SQRDMULH_advsimd_vec_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SSHR_advsimd_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void SSHR_advsimd_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void SSRA_advsimd_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void SSRA_advsimd_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void SRSHR_advsimd_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void SRSHR_advsimd_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void SRSRA_advsimd_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void SRSRA_advsimd_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void SHL_advsimd_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void SHL_advsimd_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void SQSHL_advsimd_imm_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void SQSHL_advsimd_imm_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void SQSHRN_advsimd_1(Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
void SQSHRN_advsimd_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
void SQRSHRN_advsimd_1(Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
void SQRSHRN_advsimd_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
void SCVTF_advsimd_fix_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void SCVTF_advsimd_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void FCVTZS_advsimd_fix_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void FCVTZS_advsimd_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void USHR_advsimd_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void USHR_advsimd_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void USRA_advsimd_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void USRA_advsimd_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void URSHR_advsimd_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void URSHR_advsimd_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void URSRA_advsimd_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void URSRA_advsimd_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void SRI_advsimd_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void SRI_advsimd_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void SLI_advsimd_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void SLI_advsimd_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void SQSHLU_advsimd_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void SQSHLU_advsimd_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void UQSHL_advsimd_imm_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void UQSHL_advsimd_imm_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void SQSHRUN_advsimd_1(Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
void SQSHRUN_advsimd_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
void SQRSHRUN_advsimd_1(Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
void SQRSHRUN_advsimd_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
void UQSHRN_advsimd_1(Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
void UQSHRN_advsimd_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
void UQRSHRN_advsimd_1(Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
void UQRSHRN_advsimd_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
void UCVTF_advsimd_fix_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void UCVTF_advsimd_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void FCVTZU_advsimd_fix_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void FCVTZU_advsimd_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);
void SQDMLAL_advsimd_elt_1(Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd);
void SQDMLAL_advsimd_elt_2(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd);
void SQDMLSL_advsimd_elt_1(Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd);
void SQDMLSL_advsimd_elt_2(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd);
void SQDMULL_advsimd_elt_1(Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd);
void SQDMULL_advsimd_elt_2(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd);
void SQDMULH_advsimd_elt_1(Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void SQDMULH_advsimd_elt_2(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void SQRDMULH_advsimd_elt_1(Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void SQRDMULH_advsimd_elt_2(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void FMLA_advsimd_elt_1(bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void FMLA_advsimd_elt_2(bool sz, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void FMLA_advsimd_elt_3(bool Q, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void FMLA_advsimd_elt_4(bool Q, bool sz, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void FMLS_advsimd_elt_1(bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void FMLS_advsimd_elt_2(bool sz, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void FMLS_advsimd_elt_3(bool Q, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void FMLS_advsimd_elt_4(bool Q, bool sz, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void FMUL_advsimd_elt_1(bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void FMUL_advsimd_elt_2(bool sz, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void FMUL_advsimd_elt_3(bool Q, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void FMUL_advsimd_elt_4(bool Q, bool sz, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void SQRDMLAH_advsimd_elt_1(Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void SQRDMLAH_advsimd_elt_2(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void SQRDMLSH_advsimd_elt_1(Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void SQRDMLSH_advsimd_elt_2(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void FMULX_advsimd_elt_1(bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void FMULX_advsimd_elt_2(bool sz, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void FMULX_advsimd_elt_3(bool Q, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void FMULX_advsimd_elt_4(bool Q, bool sz, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void TBL_advsimd(bool Q, Vec Vm, Imm<2> len, Vec Vn, Vec Vd);
void TBX_advsimd(bool Q, Vec Vm, Imm<2> len, Vec Vn, Vec Vd);
void UZP1_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void TRN1_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void ZIP1_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void UZP2_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void TRN2_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void ZIP2_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void EXT_advsimd(bool Q, Vec Vm, Imm<4> imm4, Vec Vn, Vec Vd);
void DUP_advsimd_gen(bool Q, Imm<5> imm5, Reg Rn, Vec Vd);
void SMOV_advsimd(bool Q, Imm<5> imm5, Vec Vn, Reg Rd);
void UMOV_advsimd(bool Q, Imm<5> imm5, Vec Vn, Reg Rd);
void INS_advsimd_gen(Imm<5> imm5, Reg Rn, Vec Vd);
void INS_advsimd_elt(Imm<5> imm5, Imm<4> imm4, Vec Vn, Vec Vd);
void FMAXNM_advsimd_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FMAXNM_advsimd_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
void FMLA_advsimd_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FMLA_advsimd_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
void FADD_advsimd_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FADD_advsimd_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
void FMAX_advsimd_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FMAX_advsimd_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
void FMINNM_advsimd_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FMINNM_advsimd_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
void FMLS_advsimd_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FMLS_advsimd_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
void FSUB_advsimd_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FSUB_advsimd_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
void FMIN_advsimd_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FMIN_advsimd_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
void FMAXNMP_advsimd_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FMAXNMP_advsimd_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
void FADDP_advsimd_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FADDP_advsimd_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
void FMUL_advsimd_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FMUL_advsimd_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
void FMAXP_advsimd_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FMAXP_advsimd_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
void FDIV_advsimd_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FDIV_advsimd_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
void FMINNMP_advsimd_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FMINNMP_advsimd_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
void FMINP_advsimd_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FMINP_advsimd_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
void FRINTN_advsimd_1(bool Q, Vec Vn, Vec Vd);
void FRINTN_advsimd_2(bool Q, bool sz, Vec Vn, Vec Vd);
void FRINTM_advsimd_1(bool Q, Vec Vn, Vec Vd);
void FRINTM_advsimd_2(bool Q, bool sz, Vec Vn, Vec Vd);
void FABS_advsimd_1(bool Q, Vec Vn, Vec Vd);
void FABS_advsimd_2(bool Q, bool sz, Vec Vn, Vec Vd);
void FRINTP_advsimd_1(bool Q, Vec Vn, Vec Vd);
void FRINTP_advsimd_2(bool Q, bool sz, Vec Vn, Vec Vd);
void FRINTZ_advsimd_1(bool Q, Vec Vn, Vec Vd);
void FRINTZ_advsimd_2(bool Q, bool sz, Vec Vn, Vec Vd);
void FRINTA_advsimd_1(bool Q, Vec Vn, Vec Vd);
void FRINTA_advsimd_2(bool Q, bool sz, Vec Vn, Vec Vd);
void FRINTX_advsimd_1(bool Q, Vec Vn, Vec Vd);
void FRINTX_advsimd_2(bool Q, bool sz, Vec Vn, Vec Vd);
void FNEG_advsimd_1(bool Q, Vec Vn, Vec Vd);
void FNEG_advsimd_2(bool Q, bool sz, Vec Vn, Vec Vd);
void FRINTI_advsimd_1(bool Q, Vec Vn, Vec Vd);
void FRINTI_advsimd_2(bool Q, bool sz, Vec Vn, Vec Vd);
void FSQRT_advsimd_1(bool Q, Vec Vn, Vec Vd);
void FSQRT_advsimd_2(bool Q, bool sz, Vec Vn, Vec Vd);
void SDOT_advsimd_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void UDOT_advsimd_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void FCMLA_advsimd_vec(bool Q, Imm<2> size, Vec Vm, Imm<2> rot, Vec Vn, Vec Vd);
void FCADD_advsimd_vec(bool Q, Imm<2> size, Vec Vm, Imm<1> rot, Vec Vn, Vec Vd);
void REV64_advsimd(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void REV16_advsimd(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void SADDLP_advsimd(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void CLS_advsimd(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void CNT_advsimd(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void SADALP_advsimd(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void XTN_advsimd(bool Q, Imm<2> size, Vec Vn, Reg Rd);
void FCVTN_advsimd(bool Q, bool sz, Vec Vn, Reg Rd);
void FCVTL_advsimd(bool Q, bool sz, Reg Rn, Vec Vd);
void URECPE_advsimd(bool Q, bool sz, Vec Vn, Vec Vd);
void REV32_advsimd(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void UADDLP_advsimd(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void CLZ_advsimd(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void UADALP_advsimd(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void SHLL_advsimd(bool Q, Imm<2> size, Reg Rn, Vec Vd);
void NOT_advsimd(bool Q, Vec Vn, Vec Vd);
void RBIT_advsimd(bool Q, Vec Vn, Vec Vd);
void URSQRTE_advsimd(bool Q, bool sz, Vec Vn, Vec Vd);
void SADDLV_advsimd(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void SMAXV_advsimd(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void SMINV_advsimd(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void ADDV_advsimd(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void FMAXNMV_advsimd_1(bool Q, Vec Vn, Vec Vd);
void FMAXNMV_advsimd_2(bool Q, bool sz, Vec Vn, Vec Vd);
void FMAXV_advsimd_1(bool Q, Vec Vn, Vec Vd);
void FMAXV_advsimd_2(bool Q, bool sz, Vec Vn, Vec Vd);
void FMINNMV_advsimd_1(bool Q, Vec Vn, Vec Vd);
void FMINNMV_advsimd_2(bool Q, bool sz, Vec Vn, Vec Vd);
void FMINV_advsimd_1(bool Q, Vec Vn, Vec Vd);
void FMINV_advsimd_2(bool Q, bool sz, Vec Vn, Vec Vd);
void UADDLV_advsimd(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void UMAXV_advsimd(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void UMINV_advsimd(bool Q, Imm<2> size, Vec Vn, Vec Vd);
void SADDL_advsimd(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
void SADDW_advsimd(bool Q, Imm<2> size, Reg Rm, Vec Vn, Vec Vd);
void SSUBL_advsimd(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
void SSUBW_advsimd(bool Q, Imm<2> size, Reg Rm, Vec Vn, Vec Vd);
void ADDHN_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Reg Rd);
void SABAL_advsimd(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
void SUBHN_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Reg Rd);
void SABDL_advsimd(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
void SMLAL_advsimd_vec(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
void SMLSL_advsimd_vec(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
void SMULL_advsimd_vec(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
void PMULL_advsimd(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
void UADDL_advsimd(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
void UADDW_advsimd(bool Q, Imm<2> size, Reg Rm, Vec Vn, Vec Vd);
void USUBL_advsimd(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
void USUBW_advsimd(bool Q, Imm<2> size, Reg Rm, Vec Vn, Vec Vd);
void RADDHN_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Reg Rd);
void UABAL_advsimd(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
void RSUBHN_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Reg Rd);
void UABDL_advsimd(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
void UMLAL_advsimd_vec(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
void UMLSL_advsimd_vec(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
void UMULL_advsimd_vec(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
void SHADD_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SRHADD_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SHSUB_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SMAX_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SMIN_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SABD_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SABA_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void MLA_advsimd_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void MUL_advsimd_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SMAXP_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void SMINP_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void ADDP_advsimd_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void FMLAL_advsimd_vec_1(bool Q, bool sz, Reg Rm, Reg Rn, Vec Vd);
void FMLAL_advsimd_vec_2(bool Q, bool sz, Reg Rm, Reg Rn, Vec Vd);
void AND_advsimd(bool Q, Vec Vm, Vec Vn, Vec Vd);
void BIC_advsimd_reg(bool Q, Vec Vm, Vec Vn, Vec Vd);
void FMLSL_advsimd_vec_1(bool Q, bool sz, Reg Rm, Reg Rn, Vec Vd);
void FMLSL_advsimd_vec_2(bool Q, bool sz, Reg Rm, Reg Rn, Vec Vd);
void ORR_advsimd_reg(bool Q, Vec Vm, Vec Vn, Vec Vd);
void ORN_advsimd(bool Q, Vec Vm, Vec Vn, Vec Vd);
void UHADD_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void URHADD_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void UHSUB_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void UMAX_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void UMIN_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void UABD_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void UABA_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void MLS_advsimd_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void PMUL_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void UMAXP_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void UMINP_advsimd(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
void EOR_advsimd(bool Q, Vec Vm, Vec Vn, Vec Vd);
void BSL_advsimd(bool Q, Vec Vm, Vec Vn, Vec Vd);
void BIT_advsimd(bool Q, Vec Vm, Vec Vn, Vec Vd);
void BIF_advsimd(bool Q, Vec Vm, Vec Vn, Vec Vd);
void MOVI_advsimd(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm<4> cmode, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Reg Rd);
void ORR_advsimd_imm(bool Q, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Reg Rd);
void FMOV_advsimd_1(bool Q, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Reg Rd);
void FMOV_advsimd_2(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Reg Rd);
void MVNI_advsimd(bool Q, Imm<1> a, Imm<1> b, Imm<1> c, Imm<4> cmode, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Reg Rd);
void BIC_advsimd_imm(bool Q, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Reg Rd);
void SHRN_advsimd(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
void RSHRN_advsimd(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd);
void SSHLL_advsimd(bool Q, Imm<4> immh, Imm<3> immb, Reg Rn, Vec Vd);
void USHLL_advsimd(bool Q, Imm<4> immh, Imm<3> immb, Reg Rn, Vec Vd);
void SMLAL_advsimd_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd);
void SMLSL_advsimd_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd);
void MUL_advsimd_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void SMULL_advsimd_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd);
void SDOT_advsimd_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void FMLAL_advsimd_elt_1(bool Q, bool sz, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd);
void FMLAL_advsimd_elt_2(bool Q, bool sz, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd);
void FMLSL_advsimd_elt_1(bool Q, bool sz, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd);
void FMLSL_advsimd_elt_2(bool Q, bool sz, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd);
void MLA_advsimd_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void UMLAL_advsimd_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd);
void MLS_advsimd_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void UMLSL_advsimd_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd);
void UMULL_advsimd_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd);
void UDOT_advsimd_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd);
void FCMLA_advsimd_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, Imm<2> rot, bool H, Vec Vn, Vec Vd);
void SM3TT1A_advsimd(Vec Vm, Imm<2> imm2, Vec Vn, Vec Vd);
void SM3TT1B_advsimd(Vec Vm, Imm<2> imm2, Vec Vn, Vec Vd);
void SM3TT2A_advsimd(Vec Vm, Imm<2> imm2, Vec Vn, Vec Vd);
void SM3TT2B_advsimd(Vec Vm, Imm<2> imm2, Vec Vn, Vec Vd);
void SHA512H_advsimd(Vec Vm, Vec Vn, Vec Vd);
void SHA512H2_advsimd(Vec Vm, Vec Vn, Vec Vd);
void SHA512SU1_advsimd(Vec Vm, Vec Vn, Vec Vd);
void RAX1_advsimd(Vec Vm, Vec Vn, Vec Vd);
void SM3PARTW1_advsimd(Vec Vm, Vec Vn, Vec Vd);
void SM3PARTW2_advsimd(Vec Vm, Vec Vn, Vec Vd);
void SM4EKEY_advsimd(Vec Vm, Vec Vn, Vec Vd);
void EOR3_advsimd(Vec Vm, Vec Va, Vec Vn, Vec Vd);
void BCAX_advsimd(Vec Vm, Vec Va, Vec Vn, Vec Vd);
void SM3SS1_advsimd(Vec Vm, Vec Va, Vec Vn, Vec Vd);
void SHA512SU0_advsimd(Vec Vn, Vec Vd);
void SM4E_advsimd(Vec Vn, Vec Vd);
void SCVTF_float_fix(bool sf, Imm<2> type, Imm<6> scale, Reg Rn, Vec Vd);
void UCVTF_float_fix(bool sf, Imm<2> type, Imm<6> scale, Reg Rn, Vec Vd);
void FCVTZS_float_fix(bool sf, Imm<2> type, Imm<6> scale, Vec Vn, Reg Rd);
void FCVTZU_float_fix(bool sf, Imm<2> type, Imm<6> scale, Vec Vn, Reg Rd);
void FCVTNS_float(bool sf, Imm<2> type, Vec Vn, Reg Rd);
void FCVTNU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd);
void SCVTF_float_int(bool sf, Imm<2> type, Reg Rn, Vec Vd);
void UCVTF_float_int(bool sf, Imm<2> type, Reg Rn, Vec Vd);
void FCVTAS_float(bool sf, Imm<2> type, Vec Vn, Reg Rd);
void FCVTAU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd);
void FMOV_float_gen(bool sf, Imm<2> type, Vec Vn, Vec Vd);
void FCVTPS_float(bool sf, Imm<2> type, Vec Vn, Reg Rd);
void FCVTPU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd);
void FCVTMS_float(bool sf, Imm<2> type, Vec Vn, Reg Rd);
void FCVTMU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd);
void FCVTZS_float_int(bool sf, Imm<2> type, Vec Vn, Reg Rd);
void FCVTZU_float_int(bool sf, Imm<2> type, Vec Vn, Reg Rd);
void FJCVTZS(Vec Vn, Reg Rd);
void FMOV_float(Imm<2> type, Vec Vn, Vec Vd);
void FABS_float(Imm<2> type, Vec Vn, Vec Vd);
void FNEG_float(Imm<2> type, Vec Vn, Vec Vd);
void FSQRT_float(Imm<2> type, Vec Vn, Vec Vd);
void FCVT_float(Imm<2> type, Imm<2> opc, Vec Vn, Vec Vd);
void FRINTN_float(Imm<2> type, Vec Vn, Vec Vd);
void FRINTP_float(Imm<2> type, Vec Vn, Vec Vd);
void FRINTM_float(Imm<2> type, Vec Vn, Vec Vd);
void FRINTZ_float(Imm<2> type, Vec Vn, Vec Vd);
void FRINTA_float(Imm<2> type, Vec Vn, Vec Vd);
void FRINTX_float(Imm<2> type, Vec Vn, Vec Vd);
void FRINTI_float(Imm<2> type, Vec Vn, Vec Vd);
void FCMP_float(Imm<2> type, Vec Vm, Vec Vn);
void FCMPE_float(Imm<2> type, Vec Vm, Vec Vn);
void FMOV_float_imm(Imm<2> type, Imm<8> imm8, Vec Vd);
void FCCMP_float(Imm<2> type, Vec Vm, Cond cond, Vec Vn, Imm<4> nzcv);
void FCCMPE_float(Imm<2> type, Vec Vm, Cond cond, Vec Vn, Imm<4> nzcv);
void FMUL_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd);
void FDIV_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd);
void FADD_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd);
void FSUB_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd);
void FMAX_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd);
void FMIN_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd);
void FMAXNM_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd);
void FMINNM_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd);
void FNMUL_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd);
void FCSEL_float(Imm<2> type, Vec Vm, Cond cond, Vec Vn, Vec Vd);
void FMADD_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd);
void FMSUB_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd);
void FNMADD_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd);
void FNMSUB_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd);
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