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/* | |
si5351 divider finder function | |
Copywrite (C) 2021, Scott Howard KD9PDP | |
License: | |
Permission is hereby granted, free of charge, to any person obtaining a copy | |
of this software and associated documentation files (the "Software"), to deal | |
in the Software without restriction, including without limitation the rights | |
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
copies of the Software, and to permit persons to whom the Software is | |
furnished to do so, subject to the following conditions: | |
The above copyright notice and this permission notice shall be included in all | |
copies or substantial portions of the Software. | |
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE | |
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
SOFTWARE. | |
*/ | |
const uint32_t FVCO_MIN = 600000000, FVCO_MAX = 900000000; | |
typedef struct { | |
uint32_t FB_a, FB_b, FB_c, MS_a, MS_b, MS_c; | |
bool FB_int, MS_int; | |
} dividerVals_t; | |
void setup() { | |
// put your setup code here, to run once: | |
Serial.begin(115200); | |
delay(1); | |
Serial.println("all for 27 MHz clock"); | |
dividerVals_t results = {0, 0, 0, 0, 0, 0, 0, 0}; | |
results = divCalc1(7000001UL, 27000000UL); // (desired, osc_clock) this one needs fractional for both | |
Serial.println("Fractional both (7000001 Hz that is 7 MHz +1)"); | |
Serial.println(results.FB_a); | |
Serial.println(results.FB_b); | |
Serial.println(results.FB_c); | |
Serial.println(results.FB_int); | |
Serial.println(results.MS_a); | |
Serial.println(results.MS_b); | |
Serial.println(results.MS_c); | |
Serial.println(results.MS_int); | |
results = divCalc1(7100000UL, 27000000UL); //this one needs fractional for just one | |
Serial.println("Fractional FB, Integer for MS (7.1 MHz)"); | |
Serial.println(results.FB_a); | |
Serial.println(results.FB_b); | |
Serial.println(results.FB_c); | |
Serial.println(results.FB_int); | |
Serial.println(results.MS_a); | |
Serial.println(results.MS_b); | |
Serial.println(results.MS_c); | |
Serial.println(results.MS_int); | |
results = divCalc1(7000000UL, 27000000UL); //this is intergers for them all | |
Serial.println("Integers for both (7 MHz)"); | |
Serial.println(results.FB_a); | |
Serial.println(results.FB_b); | |
Serial.println(results.FB_c); | |
Serial.println(results.FB_int); | |
Serial.println(results.MS_a); | |
Serial.println(results.MS_b); | |
Serial.println(results.MS_c); | |
Serial.println(results.MS_int); | |
} | |
void loop() { | |
} | |
dividerVals_t divCalc1(uint32_t desired_freq, uint32_t osc_freq) { | |
// see https://www.reddit.com/r/amateurradio/comments/lpdfpx/tutorial_how_to_find_the_exact_divider_ratios_fo/ | |
// https://gist.github.com/maqifrnswa/f83bdcf1bf73b5f656a3053282db4de3 | |
uint32_t gcdVal = 0; | |
uint64_t fvco = 0, lcmVal = 0; // if really missmatched, this can be huge | |
//uint32_t fvco_min=600000000UL; | |
dividerVals_t divider_vals = {0, 0, 1, 0, 0, 1, 0, 0}; // default of 0+0/1, and no int bit set | |
// bounds check desired_freq | |
//first try to get integer multiple for both FB and MS | |
// e.g., find a with b=0, c=1 for both | |
gcdVal = gcd(desired_freq, osc_freq); | |
lcmVal = (uint64_t)desired_freq / gcdVal * osc_freq; | |
fvco = ceilDivUL(FVCO_MIN, lcmVal) * lcmVal; | |
if (fvco <= FVCO_MAX && fvco >= FVCO_MIN) { // first try to see if both FB and MS can use integer division. If clock is even, output always even | |
divider_vals.FB_a = fvco / osc_freq; | |
divider_vals.FB_int = !(0b1L & divider_vals.FB_a); // set to True if even integer | |
divider_vals.MS_a = fvco / desired_freq; | |
divider_vals.MS_int = !(0b1L & divider_vals.MS_a); // set to True if even integer | |
} else { //if (osc_freq / gcdVal <= 1048757UL) { // next try to keep MS an even integer and FB fractional | |
divider_vals.MS_a = FVCO_MAX / desired_freq; //set VCO to the highest recommended value. | |
// The VCO can actually be any valid freq. ClockBuilder chooses 900MHz, so I will too. | |
// But if there's intereference, you can pick another one. | |
divider_vals.MS_a &= 0xFFFFFFFEUL; // make multiplier even | |
divider_vals.MS_int = 1; | |
divider_vals.FB_c = osc_freq / gcdVal; | |
uint32_t x = desired_freq * divider_vals.MS_a / gcdVal; | |
ldiv_t xDivY = ldiv(x, divider_vals.FB_c); | |
uint32_t gcdTemp = gcd(xDivY.rem, divider_vals.FB_c); | |
divider_vals.FB_a = xDivY.quot; | |
divider_vals.FB_b = xDivY.rem / gcdTemp; // is guaranteed to be non-zero, otherwise first part of if statement would have worked. | |
divider_vals.FB_c = divider_vals.FB_c / gcdTemp; | |
} | |
// below block should rarely happen. I'm strugglying trying to find a case where it does! | |
if (divider_vals.FB_c > 1048757UL) { // Make both FB and MS fractional. The denominator would have been too big for keeping MS as an integer | |
// fvco/desired_freq = x/y. When reduced, denominator must be < 1048757 | |
// Find LCM (will be greater than 900 MHz because of first step in if statement checks) | |
// if LCM > 900, divide LCM by integers that yield integer output until between 600-900, then that's your fvco | |
// if less than 600, multiply with integers until 600-900 | |
// e.g, while (fvco >900 or < 600) | |
// If > 900 | |
// find ratio between fvco and 900. truncate is ok to get integer. | |
// Find integer > than that integer that fvco is wholy divisibly by that integer | |
// divide by that integer | |
// if < 600 | |
// find ratio between fvco and 600. use ciel. multiply fvco by that value | |
while (fvco > FVCO_MAX || fvco < FVCO_MIN) { | |
fvco = lcmVal; // make the starting point for the fvco the lcmVal | |
uint32_t rat = fvco / FVCO_MAX; | |
while (fvco > FVCO_MAX) { | |
rat++; // increment first since it was truncated earlier | |
if (!(fvco % rat)) fvco = fvco / rat; | |
} | |
if (fvco < FVCO_MIN) fvco = ceilDivUL(FVCO_MIN, fvco) * fvco; | |
// MAYBE BUG: this could oscillate between two values. e.g., fvco= 1000, 1000/900 = 1. rat++=2. 1000/2 = 500. Then ceil(600/500) = 2. | |
// 500*2 = 1000. Back to the begnning, it will just bounch back and forth. | |
if (fvco < 2 * FVCO_MIN && fvco > FVCO_MAX) fvco = fvco * 10; // try to "knock" it out of "no man's land" where it will oscilate. | |
} | |
// MS settings - we found a fvco that makes this work - now let's find settings: | |
// this is just copied - so maybe something we can do with a function | |
uint32_t gcdTemp = gcd(osc_freq, fvco); | |
ldiv_t xDivY = ldiv(fvco, osc_freq); | |
divider_vals.FB_a = xDivY.quot; | |
divider_vals.FB_b = xDivY.rem / gcdTemp; // is guaranteed to be non-zero, otherwise first part of if statement would have worked. | |
divider_vals.FB_c = osc_freq / gcdTemp; //FBgcd; | |
gcdTemp = gcd(desired_freq, fvco); | |
xDivY = ldiv(fvco, desired_freq); | |
divider_vals.MS_a = xDivY.quot; | |
divider_vals.MS_b = xDivY.rem / gcdTemp; // is guaranteed to be non-zero, otherwise first part of if statement would have worked. | |
divider_vals.MS_c = desired_freq / gcdTemp; //FBgcd; | |
} | |
return divider_vals; | |
} | |
uint32_t ceilDivUL(uint32_t a, uint32_t b) { | |
// Performs ceil(a/b) when a and b are unsigned long ints | |
return (a - 1) / b + 1; | |
} | |
//uint32_t lcm(uint32_t a, uint32_t b) { | |
// return a/gcd(a, b)*b; | |
//} | |
uint32_t gcd(uint32_t u, uint32_t v) { | |
int shift; | |
if (u == 0) return v; | |
if (v == 0) return u; | |
shift = __builtin_ctzl(u | v); | |
while ( !(u & 0b1L)) u >>= 1; // manual u >>= __buitin_ctzl(u) | |
while (v ) { | |
while ( !(v & 0b1L)) v >>= 1; | |
if (u > v) { | |
uint32_t t = v; | |
v = u; | |
u = t; | |
} | |
v = v - u; | |
} | |
return u << shift; | |
} |
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