2021-05-09 by kbeckmann
These are my notes of how I interpret how the clock tree works in Caravel. It might be inaccurate.
caravel:
- chip_io: padframe
- user_project_wrapper: mprj
- mgmt_core: soc
- caravel_clocking: clocking
- digital_pll: pll
- mgmt_soc: soc
ext_clk_sel = 0; // Use PLL
caravel.clock -> caravel.clock_core -> soc.clock -> digital_pll -> pll_clk -> clocking -> pll.clockp[0] -> core_clk
\> pll_clk90 -> clocking -> pll.clockp[1] -> user_clk
ext_clk_sel = 1; // Use external clock pin for both core_clk and user_clk
caravel.clock -> caravel.clock_core -> soc.clock -> clocking -> core_ext_clk -> core_clk
\> user_clk
core_clk -> caravel_clk -> mprj_clock
user_clk -> caravel_clk2 -> mprj_clock2
// caravel/verilog/rtl/caravel.v:
// Caravel top module
module caravel (
input clock, // CMOS core clock input, not a crystal
input resetb, // reset, active low
);
// caravel/verilog/rtl/chip_io.v:
chip_io padframe (
// Package Pins
.clock(clock),
.resetb(resetb),
// SoC Core Interface
.resetb_core_h(rstb_h), // 3.3V
.clock_core(clock_core),
);
wire rstb_h; // 3.3V Reset signal from "resetb" pad
wire rstb_l; // 1.8V Reset signal from "resetb" pad
wire clock_core; // from "clock" pad
wire caravel_clk; // core_clk output from mgmt_core
wire caravel_clk2; // user_clk output from mgmt_core
wire caravel_rstn; // core_rstn output from mgmt_core
// caravel/verilog/rtl/mgmt_core.v:
mgmt_core soc (
// Master Reset
.resetb(rstb_l), // input
.porb(porb_l), // input
// Clocks and reset
.clock(clock_core), // input
.core_clk(caravel_clk), // output
.user_clk(caravel_clk2), // output
.core_rstn(caravel_rstn), // output
);
// caravel/verilog/rtl/caravel_clocking.v:
caravel_clocking clocking (
.resetb(resetb), // input
.resetb_sync(core_rstn), // output propagated and buffered reset
.ext_clk_sel(ext_clk_sel), // input 0=use PLL clock, 1=use external (pad) clock
.ext_clk(clock), // input External pad (slow) clock
.pll_clk(pll_clk), // input Internal PLL (fast) clock (divider1)
.pll_clk90(pll_clk90), // input Internal PLL (fast) clock (divider2), 90 degree phase
.core_clk(core_clk), // output core clock
.user_clk(user_clk), // output user (secondary) clock
);
// caravel/verilog/rtl/mgmt_soc.v:
mgmt_soc soc (
.resetn(core_rstn),
.clk(core_clk),
.user_clk(user_clk),
);
user_project_wrapper mprj (
.wb_clk_i(mprj_clock),
.wb_rst_i(mprj_reset),
.user_clock2(mprj_clock2)
);