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kbeckmann/blinky.py

Last active November 9, 2020 20:53
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blinky.py
from nmigen import *
from nmigen.build import *
from nmigen_boards.tang_nano import TangNanoPlatform
class Blinky(Elaboratable):
def elaborate(self, platform):
m = Module()
platform.add_resources([
Resource("led", 0, Pins("18", dir="o"),
Attrs(IOSTANDARD="LVCMOS33")),
])
led = platform.request("led")
clk_freq = platform.default_clk_frequency
led_counter = Signal(range(int(clk_freq//2)), reset=int(clk_freq//2) - 1)
with m.If(led_counter == 0):
m.d.sync += led_counter.eq(led_counter.reset)
m.d.sync += led.eq(~led.o)
with m.Else():
m.d.sync += led_counter.eq(led_counter - 1)
return m
if __name__ == "__main__":
p = TangNanoPlatform()
p.build(Blinky(), do_program=True)
Raw
out.log
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.9+3656 (git sha1 dfeff65c, gcc 10.2.0 -march=x86-64 -mtune=generic -O2 -fstack-protector-strong -fno-plt -fPIC -Os)
-- Executing script file `top.ys' --
1. Executing Verilog-2005 frontend: top.debug.v
Parsing Verilog input from `top.debug.v' to AST representation.
Generating RTLIL representation for module `\cd_sync'.
Generating RTLIL representation for module `\pin_clk24_0'.
Generating RTLIL representation for module `\pin_led_0'.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.
2. Executing SYNTH_GOWIN pass.
2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/gowin/cells_sim.v
Parsing Verilog input from `/usr/bin/../share/yosys/gowin/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT1'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\LUT3'.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\__APICULA_LUT5'.
Generating RTLIL representation for module `\__APICULA_LUT6'.
Generating RTLIL representation for module `\__APICULA_LUT7'.
Generating RTLIL representation for module `\__APICULA_LUT8'.
Generating RTLIL representation for module `\MUX2'.
Generating RTLIL representation for module `\MUX2_LUT5'.
Generating RTLIL representation for module `\MUX2_LUT6'.
Generating RTLIL representation for module `\MUX2_LUT7'.
Generating RTLIL representation for module `\MUX2_LUT8'.
Generating RTLIL representation for module `\DFF'.
Generating RTLIL representation for module `\DFFE'.
Generating RTLIL representation for module `\DFFS'.
Generating RTLIL representation for module `\DFFSE'.
Generating RTLIL representation for module `\DFFR'.
Generating RTLIL representation for module `\DFFRE'.
Generating RTLIL representation for module `\DFFP'.
Generating RTLIL representation for module `\DFFPE'.
Generating RTLIL representation for module `\DFFC'.
Generating RTLIL representation for module `\DFFCE'.
Generating RTLIL representation for module `\DFFN'.
Generating RTLIL representation for module `\DFFNE'.
Generating RTLIL representation for module `\DFFNS'.
Generating RTLIL representation for module `\DFFNSE'.
Generating RTLIL representation for module `\DFFNR'.
Generating RTLIL representation for module `\DFFNRE'.
Generating RTLIL representation for module `\DFFNP'.
Generating RTLIL representation for module `\DFFNPE'.
Generating RTLIL representation for module `\DFFNC'.
Generating RTLIL representation for module `\DFFNCE'.
Generating RTLIL representation for module `\VCC'.
Generating RTLIL representation for module `\GND'.
Generating RTLIL representation for module `\IBUF'.
Generating RTLIL representation for module `\OBUF'.
Generating RTLIL representation for module `\TBUF'.
Generating RTLIL representation for module `\IOBUF'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\ALU'.
Generating RTLIL representation for module `\RAM16S4'.
Generating RTLIL representation for module `\SDP'.
Successfully finished Verilog frontend.
2.2. Executing HIERARCHY pass (managing design hierarchy).
2.2.1. Analyzing design hierarchy..
Top module: \top
Used module: \pin_led_0
Used module: \pin_clk24_0
Used module: \cd_sync
2.2.2. Analyzing design hierarchy..
Top module: \top
Used module: \pin_led_0
Used module: \pin_clk24_0
Used module: \cd_sync
Removed 0 unused modules.
2.3. Executing PROC pass (convert processes to netlists).
2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\ALU.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:630$220'.
Found and cleaned up 1 empty switch in `\top.$proc$top.debug.v:170$26'.
Found and cleaned up 1 empty switch in `\top.$proc$top.debug.v:152$22'.
Found and cleaned up 1 empty switch in `\cd_sync.$proc$top.debug.v:52$10'.
Found and cleaned up 1 empty switch in `\cd_sync.$proc$top.debug.v:42$7'.
Cleaned up 5 empty switches.
2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/gowin/cells_sim.v:535$216 in module DFFNCE.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/gowin/cells_sim.v:515$214 in module DFFNC.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/gowin/cells_sim.v:496$212 in module DFFNPE.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/gowin/cells_sim.v:476$210 in module DFFNP.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/gowin/cells_sim.v:457$208 in module DFFNRE.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/gowin/cells_sim.v:437$206 in module DFFNR.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/gowin/cells_sim.v:418$204 in module DFFNSE.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/gowin/cells_sim.v:398$202 in module DFFNS.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/gowin/cells_sim.v:348$196 in module DFFCE.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/gowin/cells_sim.v:328$194 in module DFFC.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/gowin/cells_sim.v:309$192 in module DFFPE.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/gowin/cells_sim.v:289$190 in module DFFP.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/gowin/cells_sim.v:270$188 in module DFFRE.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/gowin/cells_sim.v:250$186 in module DFFR.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/gowin/cells_sim.v:231$184 in module DFFSE.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/gowin/cells_sim.v:211$182 in module DFFS.
Marked 2 switch rules as full_case in process $proc$top.debug.v:170$26 in module top.
Marked 1 switch rules as full_case in process $proc$top.debug.v:152$22 in module top.
Marked 1 switch rules as full_case in process $proc$top.debug.v:42$7 in module cd_sync.
Removed a total of 0 dead cases.
2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 8 redundant assignments.
Promoted 40 assignments to connections.
2.3.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\DFFNCE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$217'.
Set init value: \Q = 1'0
Found init rule in `\DFFNC.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$215'.
Set init value: \Q = 1'0
Found init rule in `\DFFNPE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$213'.
Set init value: \Q = 1'1
Found init rule in `\DFFNP.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$211'.
Set init value: \Q = 1'1
Found init rule in `\DFFNRE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$209'.
Set init value: \Q = 1'0
Found init rule in `\DFFNR.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$207'.
Set init value: \Q = 1'0
Found init rule in `\DFFNSE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$205'.
Set init value: \Q = 1'1
Found init rule in `\DFFNS.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$203'.
Set init value: \Q = 1'1
Found init rule in `\DFFNE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$201'.
Set init value: \Q = 1'0
Found init rule in `\DFFN.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$199'.
Set init value: \Q = 1'0
Found init rule in `\DFFCE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$197'.
Set init value: \Q = 1'0
Found init rule in `\DFFC.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$195'.
Set init value: \Q = 1'0
Found init rule in `\DFFPE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$193'.
Set init value: \Q = 1'1
Found init rule in `\DFFP.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$191'.
Set init value: \Q = 1'1
Found init rule in `\DFFRE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$189'.
Set init value: \Q = 1'0
Found init rule in `\DFFR.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$187'.
Set init value: \Q = 1'0
Found init rule in `\DFFSE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$185'.
Set init value: \Q = 1'1
Found init rule in `\DFFS.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$183'.
Set init value: \Q = 1'1
Found init rule in `\DFFE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$181'.
Set init value: \Q = 1'0
Found init rule in `\DFF.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$179'.
Set init value: \Q = 1'0
Found init rule in `\top.$proc$top.debug.v:126$32'.
Set init value: \pin_led_0_led_0__o = 1'0
Found init rule in `\top.$proc$top.debug.v:122$31'.
Set init value: \led_counter = 24'101101110001101011111111
Found init rule in `\cd_sync.$proc$top.debug.v:31$15'.
Set init value: \timer = 9'000000000
Found init rule in `\cd_sync.$proc$top.debug.v:25$14'.
Set init value: \ready = 1'0
2.3.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \CLEAR in `\DFFNCE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:535$216'.
Found async reset \CLEAR in `\DFFNC.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:515$214'.
Found async reset \PRESET in `\DFFNPE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:496$212'.
Found async reset \PRESET in `\DFFNP.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:476$210'.
Found async reset \CLEAR in `\DFFCE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:348$196'.
Found async reset \CLEAR in `\DFFC.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:328$194'.
Found async reset \PRESET in `\DFFPE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:309$192'.
Found async reset \PRESET in `\DFFP.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:289$190'.
2.3.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\ALU.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:630$220'.
Creating decoders for process `\DFFNCE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$217'.
Creating decoders for process `\DFFNCE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:535$216'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFNC.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$215'.
Creating decoders for process `\DFFNC.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:515$214'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFNPE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$213'.
Creating decoders for process `\DFFNPE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:496$212'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFNP.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$211'.
Creating decoders for process `\DFFNP.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:476$210'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFNRE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$209'.
Creating decoders for process `\DFFNRE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:457$208'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFNR.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$207'.
Creating decoders for process `\DFFNR.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:437$206'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFNSE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$205'.
Creating decoders for process `\DFFNSE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:418$204'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFNS.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$203'.
Creating decoders for process `\DFFNS.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:398$202'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFNE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$201'.
Creating decoders for process `\DFFNE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:381$200'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFN.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$199'.
Creating decoders for process `\DFFN.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:366$198'.
Creating decoders for process `\DFFCE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$197'.
Creating decoders for process `\DFFCE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:348$196'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFC.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$195'.
Creating decoders for process `\DFFC.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:328$194'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFPE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$193'.
Creating decoders for process `\DFFPE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:309$192'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFP.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$191'.
Creating decoders for process `\DFFP.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:289$190'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFRE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$189'.
Creating decoders for process `\DFFRE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:270$188'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFR.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$187'.
Creating decoders for process `\DFFR.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:250$186'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFSE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$185'.
Creating decoders for process `\DFFSE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:231$184'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFS.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$183'.
Creating decoders for process `\DFFS.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:211$182'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$181'.
Creating decoders for process `\DFFE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:194$180'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFF.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$179'.
Creating decoders for process `\DFF.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:179$178'.
Creating decoders for process `\top.$proc$top.debug.v:126$32'.
Creating decoders for process `\top.$proc$top.debug.v:122$31'.
Creating decoders for process `\top.$proc$top.debug.v:102$30'.
Creating decoders for process `\top.$proc$top.debug.v:170$26'.
1/2: $2\pin_led_0_led_0__o$next[0:0]$29
2/2: $1\pin_led_0_led_0__o$next[0:0]$28
Creating decoders for process `\top.$proc$top.debug.v:152$22'.
1/2: $2\led_counter$next[23:0]$25
2/2: $1\led_counter$next[23:0]$24
Creating decoders for process `\top.$proc$top.debug.v:137$21'.
Creating decoders for process `\top.$proc$top.debug.v:135$20'.
Creating decoders for process `\cd_sync.$proc$top.debug.v:31$15'.
Creating decoders for process `\cd_sync.$proc$top.debug.v:25$14'.
Creating decoders for process `\cd_sync.$proc$top.debug.v:7$13'.
Creating decoders for process `\cd_sync.$proc$top.debug.v:52$10'.
1/1: $1\timer$next[8:0]$12
Creating decoders for process `\cd_sync.$proc$top.debug.v:42$7'.
1/1: $1\ready$next[0:0]$9
Creating decoders for process `\cd_sync.$proc$top.debug.v:40$6'.
Creating decoders for process `\cd_sync.$proc$top.debug.v:38$5'.
2.3.7. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `\top.\initial' from process `\top.$proc$top.debug.v:102$30'.
No latch inferred for signal `\top.\pin_led_0_led_0__o$next' from process `\top.$proc$top.debug.v:170$26'.
No latch inferred for signal `\top.\led_counter$next' from process `\top.$proc$top.debug.v:152$22'.
No latch inferred for signal `\cd_sync.\initial' from process `\cd_sync.$proc$top.debug.v:7$13'.
No latch inferred for signal `\cd_sync.\timer$next' from process `\cd_sync.$proc$top.debug.v:52$10'.
No latch inferred for signal `\cd_sync.\ready$next' from process `\cd_sync.$proc$top.debug.v:42$7'.
2.3.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\ALU.\C' using process `\ALU.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:630$220'.
created direct connection (no actual register cell created).
Creating register for signal `\ALU.\S' using process `\ALU.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:630$220'.
created direct connection (no actual register cell created).
Creating register for signal `\DFFNCE.\Q' using process `\DFFNCE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:535$216'.
created $adff cell `$procdff$292' with negative edge clock and positive level reset.
Creating register for signal `\DFFNC.\Q' using process `\DFFNC.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:515$214'.
created $adff cell `$procdff$293' with negative edge clock and positive level reset.
Creating register for signal `\DFFNPE.\Q' using process `\DFFNPE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:496$212'.
created $adff cell `$procdff$294' with negative edge clock and positive level reset.
Creating register for signal `\DFFNP.\Q' using process `\DFFNP.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:476$210'.
created $adff cell `$procdff$295' with negative edge clock and positive level reset.
Creating register for signal `\DFFNRE.\Q' using process `\DFFNRE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:457$208'.
created $dff cell `$procdff$296' with negative edge clock.
Creating register for signal `\DFFNR.\Q' using process `\DFFNR.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:437$206'.
created $dff cell `$procdff$297' with negative edge clock.
Creating register for signal `\DFFNSE.\Q' using process `\DFFNSE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:418$204'.
created $dff cell `$procdff$298' with negative edge clock.
Creating register for signal `\DFFNS.\Q' using process `\DFFNS.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:398$202'.
created $dff cell `$procdff$299' with negative edge clock.
Creating register for signal `\DFFNE.\Q' using process `\DFFNE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:381$200'.
created $dff cell `$procdff$300' with negative edge clock.
Creating register for signal `\DFFN.\Q' using process `\DFFN.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:366$198'.
created $dff cell `$procdff$301' with negative edge clock.
Creating register for signal `\DFFCE.\Q' using process `\DFFCE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:348$196'.
created $adff cell `$procdff$302' with positive edge clock and positive level reset.
Creating register for signal `\DFFC.\Q' using process `\DFFC.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:328$194'.
created $adff cell `$procdff$303' with positive edge clock and positive level reset.
Creating register for signal `\DFFPE.\Q' using process `\DFFPE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:309$192'.
created $adff cell `$procdff$304' with positive edge clock and positive level reset.
Creating register for signal `\DFFP.\Q' using process `\DFFP.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:289$190'.
created $adff cell `$procdff$305' with positive edge clock and positive level reset.
Creating register for signal `\DFFRE.\Q' using process `\DFFRE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:270$188'.
created $dff cell `$procdff$306' with positive edge clock.
Creating register for signal `\DFFR.\Q' using process `\DFFR.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:250$186'.
created $dff cell `$procdff$307' with positive edge clock.
Creating register for signal `\DFFSE.\Q' using process `\DFFSE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:231$184'.
created $dff cell `$procdff$308' with positive edge clock.
Creating register for signal `\DFFS.\Q' using process `\DFFS.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:211$182'.
created $dff cell `$procdff$309' with positive edge clock.
Creating register for signal `\DFFE.\Q' using process `\DFFE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:194$180'.
created $dff cell `$procdff$310' with positive edge clock.
Creating register for signal `\DFF.\Q' using process `\DFF.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:179$178'.
created $dff cell `$procdff$311' with positive edge clock.
Creating register for signal `\top.\led_counter' using process `\top.$proc$top.debug.v:137$21'.
created $dff cell `$procdff$312' with positive edge clock.
Creating register for signal `\top.\pin_led_0_led_0__o' using process `\top.$proc$top.debug.v:135$20'.
created $dff cell `$procdff$313' with positive edge clock.
Creating register for signal `\cd_sync.\ready' using process `\cd_sync.$proc$top.debug.v:40$6'.
created $dff cell `$procdff$314' with positive edge clock.
Creating register for signal `\cd_sync.\timer' using process `\cd_sync.$proc$top.debug.v:38$5'.
created $dff cell `$procdff$315' with positive edge clock.
2.3.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `ALU.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:630$220'.
Removing empty process `DFFNCE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$217'.
Found and cleaned up 1 empty switch in `\DFFNCE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:535$216'.
Removing empty process `DFFNCE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:535$216'.
Removing empty process `DFFNC.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$215'.
Removing empty process `DFFNC.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:515$214'.
Removing empty process `DFFNPE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$213'.
Found and cleaned up 1 empty switch in `\DFFNPE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:496$212'.
Removing empty process `DFFNPE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:496$212'.
Removing empty process `DFFNP.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$211'.
Removing empty process `DFFNP.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:476$210'.
Removing empty process `DFFNRE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$209'.
Found and cleaned up 2 empty switches in `\DFFNRE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:457$208'.
Removing empty process `DFFNRE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:457$208'.
Removing empty process `DFFNR.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$207'.
Found and cleaned up 1 empty switch in `\DFFNR.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:437$206'.
Removing empty process `DFFNR.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:437$206'.
Removing empty process `DFFNSE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$205'.
Found and cleaned up 2 empty switches in `\DFFNSE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:418$204'.
Removing empty process `DFFNSE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:418$204'.
Removing empty process `DFFNS.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$203'.
Found and cleaned up 1 empty switch in `\DFFNS.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:398$202'.
Removing empty process `DFFNS.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:398$202'.
Removing empty process `DFFNE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$201'.
Found and cleaned up 1 empty switch in `\DFFNE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:381$200'.
Removing empty process `DFFNE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:381$200'.
Removing empty process `DFFN.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$199'.
Removing empty process `DFFN.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:366$198'.
Removing empty process `DFFCE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$197'.
Found and cleaned up 1 empty switch in `\DFFCE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:348$196'.
Removing empty process `DFFCE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:348$196'.
Removing empty process `DFFC.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$195'.
Removing empty process `DFFC.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:328$194'.
Removing empty process `DFFPE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$193'.
Found and cleaned up 1 empty switch in `\DFFPE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:309$192'.
Removing empty process `DFFPE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:309$192'.
Removing empty process `DFFP.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$191'.
Removing empty process `DFFP.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:289$190'.
Removing empty process `DFFRE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$189'.
Found and cleaned up 2 empty switches in `\DFFRE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:270$188'.
Removing empty process `DFFRE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:270$188'.
Removing empty process `DFFR.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$187'.
Found and cleaned up 1 empty switch in `\DFFR.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:250$186'.
Removing empty process `DFFR.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:250$186'.
Removing empty process `DFFSE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$185'.
Found and cleaned up 2 empty switches in `\DFFSE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:231$184'.
Removing empty process `DFFSE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:231$184'.
Removing empty process `DFFS.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$183'.
Found and cleaned up 1 empty switch in `\DFFS.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:211$182'.
Removing empty process `DFFS.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:211$182'.
Removing empty process `DFFE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$181'.
Found and cleaned up 1 empty switch in `\DFFE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:194$180'.
Removing empty process `DFFE.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:194$180'.
Removing empty process `DFF.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:0$179'.
Removing empty process `DFF.$proc$/usr/bin/../share/yosys/gowin/cells_sim.v:179$178'.
Removing empty process `top.$proc$top.debug.v:126$32'.
Removing empty process `top.$proc$top.debug.v:122$31'.
Removing empty process `top.$proc$top.debug.v:102$30'.
Found and cleaned up 2 empty switches in `\top.$proc$top.debug.v:170$26'.
Removing empty process `top.$proc$top.debug.v:170$26'.
Found and cleaned up 2 empty switches in `\top.$proc$top.debug.v:152$22'.
Removing empty process `top.$proc$top.debug.v:152$22'.
Removing empty process `top.$proc$top.debug.v:137$21'.
Removing empty process `top.$proc$top.debug.v:135$20'.
Removing empty process `cd_sync.$proc$top.debug.v:31$15'.
Removing empty process `cd_sync.$proc$top.debug.v:25$14'.
Removing empty process `cd_sync.$proc$top.debug.v:7$13'.
Found and cleaned up 1 empty switch in `\cd_sync.$proc$top.debug.v:52$10'.
Removing empty process `cd_sync.$proc$top.debug.v:52$10'.
Found and cleaned up 1 empty switch in `\cd_sync.$proc$top.debug.v:42$7'.
Removing empty process `cd_sync.$proc$top.debug.v:42$7'.
Removing empty process `cd_sync.$proc$top.debug.v:40$6'.
Removing empty process `cd_sync.$proc$top.debug.v:38$5'.
Cleaned up 24 empty switches.
2.4. Executing FLATTEN pass (flatten design).
Deleting now unused module pin_led_0.
Deleting now unused module pin_clk24_0.
Deleting now unused module cd_sync.
<suppressed ~3 debug messages>
2.5. Executing TRIBUF pass.
2.6. Executing DEMINOUT pass (demote inout ports to input or output).
2.7. Executing SYNTH pass.
2.7.1. Executing PROC pass (convert processes to netlists).
2.7.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.7.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.7.1.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.
2.7.1.4. Executing PROC_INIT pass (extract init attributes).
2.7.1.5. Executing PROC_ARST pass (detect async resets in processes).
2.7.1.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
2.7.1.7. Executing PROC_DLATCH pass (convert process syncs to latches).
2.7.1.8. Executing PROC_DFF pass (convert process syncs to FFs).
2.7.1.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.7.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~4 debug messages>
2.7.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 42 unused wires.
<suppressed ~4 debug messages>
2.7.4. Executing CHECK pass (checking for obvious problems).
checking module top..
found and reported 0 problems.
2.7.5. Executing OPT pass (performing simple optimizations).
2.7.5.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.7.5.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.
2.7.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~4 debug messages>
2.7.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
2.7.5.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.7.5.6. Executing OPT_DFF pass (perform DFF optimizations).
2.7.5.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>
2.7.5.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.7.5.9. Rerunning OPT passes. (Maybe there is more to do..)
2.7.5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~4 debug messages>
2.7.5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
2.7.5.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.7.5.13. Executing OPT_DFF pass (perform DFF optimizations).
2.7.5.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.7.5.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.7.5.16. Finished OPT passes. (There is nothing left to do.)
2.7.6. Executing FSM pass (extract and optimize FSM).
2.7.6.1. Executing FSM_DETECT pass (finding FSMs in design).
2.7.6.2. Executing FSM_EXTRACT pass (extracting FSM from design).
2.7.6.3. Executing FSM_OPT pass (simple optimizations of FSMs).
2.7.6.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.7.6.5. Executing FSM_OPT pass (simple optimizations of FSMs).
2.7.6.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
2.7.6.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
2.7.6.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
2.7.7. Executing OPT pass (performing simple optimizations).
2.7.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.7.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.7.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~4 debug messages>
2.7.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
2.7.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.7.7.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $procdff$313 ($dff) from module top (D = $1\pin_led_0_led_0__o$next[0:0]$28, Q = \pin_led_0_led_0__o, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$316 ($sdff) from module top (D = \$8, Q = \pin_led_0_led_0__o).
Adding SRST signal on $procdff$312 ($dff) from module top (D = \$3 [23:0], Q = \led_counter, rval = 24'101101110001101011111111).
Adding EN signal on $flatten\cd_sync.$procdff$315 ($dff) from module top (D = \cd_sync.$5 [8:0], Q = \cd_sync.timer).
Adding EN signal on $flatten\cd_sync.$procdff$314 ($dff) from module top (D = 1'1, Q = \cd_sync.ready).
2.7.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 6 unused cells and 6 unused wires.
<suppressed ~11 debug messages>
2.7.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.7.7.9. Rerunning OPT passes. (Maybe there is more to do..)
2.7.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
2.7.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
2.7.7.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.7.7.13. Executing OPT_DFF pass (perform DFF optimizations).
2.7.7.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.7.7.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.7.7.16. Finished OPT passes. (There is nothing left to do.)
2.7.8. Executing WREDUCE pass (reducing word size of cells).
Removed top 1 bits (of 25) from port Y of cell top.$sub$top.debug.v:132$17 ($sub).
Removed top 1 bits (of 10) from port Y of cell top.$flatten\cd_sync.$add$top.debug.v:36$3 ($add).
Removed top 1 bits (of 25) from wire top.\$3.
2.7.9. Executing PEEPOPT pass (run peephole optimizers).
2.7.10. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>
2.7.11. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
creating $macc model for $flatten\cd_sync.$add$top.debug.v:36$3 ($add).
creating $macc model for $sub$top.debug.v:132$17 ($sub).
creating $alu model for $macc $sub$top.debug.v:132$17.
creating $alu model for $macc $flatten\cd_sync.$add$top.debug.v:36$3.
creating $alu cell for $flatten\cd_sync.$add$top.debug.v:36$3: $auto$alumacc.cc:485:replace_alu$326
creating $alu cell for $sub$top.debug.v:132$17: $auto$alumacc.cc:485:replace_alu$329
created 2 $alu and 0 $macc cells.
2.7.12. Executing SHARE pass (SAT-based resource sharing).
2.7.13. Executing OPT pass (performing simple optimizations).
2.7.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.7.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.7.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
2.7.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
2.7.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.7.13.6. Executing OPT_DFF pass (perform DFF optimizations).
2.7.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.7.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.7.13.9. Finished OPT passes. (There is nothing left to do.)
2.7.14. Executing MEMORY pass.
2.7.14.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.
2.7.14.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
2.7.14.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.7.14.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
2.7.14.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.7.14.6. Executing MEMORY_COLLECT pass (generating $mem cells).
2.7.15. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.8. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
2.9. Executing TECHMAP pass (map to technology primitives).
2.9.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/gowin/brams_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/gowin/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__GW1NR_SDP'.
Successfully finished Verilog frontend.
2.9.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~3 debug messages>
2.10. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
2.11. Executing TECHMAP pass (map to technology primitives).
2.11.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/gowin/lutrams_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/gowin/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__GW1NR_RAM16S4'.
Successfully finished Verilog frontend.
2.11.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~3 debug messages>
2.12. Executing SETUNDEF pass (replace undef values with defined constants).
2.13. Executing OPT pass (performing simple optimizations).
2.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~2 debug messages>
2.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.13.3. Executing OPT_DFF pass (perform DFF optimizations).
2.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.13.5. Finished fast OPT passes.
2.14. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
2.15. Executing OPT pass (performing simple optimizations).
2.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
2.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
2.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.15.6. Executing OPT_DFF pass (perform DFF optimizations).
2.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.15.9. Finished OPT passes. (There is nothing left to do.)
2.16. Executing TECHMAP pass (map to technology primitives).
2.16.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
2.16.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/gowin/arith_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/gowin/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_gw1n_alu'.
Successfully finished Verilog frontend.
2.16.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $not.
Using template $paramod\_80_gw1n_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=9\Y_WIDTH=9 for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $dffe.
Using template $paramod\_80_gw1n_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=24\B_WIDTH=1\Y_WIDTH=24 for cells of type $alu.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $pos.
No more expansions possible.
<suppressed ~155 debug messages>
2.17. Executing OPT pass (performing simple optimizations).
2.17.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~86 debug messages>
2.17.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.17.3. Executing OPT_DFF pass (perform DFF optimizations).
2.17.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 3 unused cells and 67 unused wires.
<suppressed ~4 debug messages>
2.17.5. Finished fast OPT passes.
2.18. Executing SPLITNETS pass (splitting up multi-bit signals).
2.19. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 34 unused wires.
<suppressed ~1 debug messages>
2.20. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
2.21. Executing TECHMAP pass (map to technology primitives).
2.21.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/gowin/cells_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/gowin/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.
2.21.2. Continuing TECHMAP pass.
Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
No more expansions possible.
<suppressed ~58 debug messages>
2.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.23. Executing SIMPLEMAP pass (map simple cells to gate primitives).
2.24. Executing ABC pass (technology mapping using ABC).
2.24.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
Extracted 42 gates and 77 wires to a netlist network with 35 inputs and 6 outputs.
2.24.1.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC:
ABC: + read_blif <abc-temp-dir>/input.blif
ABC: + read_lut <abc-temp-dir>/lutdefs.txt
ABC: + strash
ABC: + ifraig
ABC: + scorr
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2
ABC: + dretime
ABC: + strash
ABC: + dch -f
ABC: + if
ABC: + mfs2
ABC: + write_blif <abc-temp-dir>/output.blif
2.24.1.2. Re-integrating ABC results.
ABC RESULTS: $lut cells: 14
ABC RESULTS: internal signals: 36
ABC RESULTS: input signals: 35
ABC RESULTS: output signals: 6
Removing temp directory.
Removed 0 unused cells and 254 unused wires.
2.25. Executing TECHMAP pass (map to technology primitives).
2.25.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/gowin/cells_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/gowin/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.
2.25.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=3\LUT=8'00000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000001 for cells of type $lut.
Using template $paramod$22d7684eb9972f1be00cdd1834c8cd0d4e21aecc\$lut for cells of type $lut.
Using template $paramod$5fba6fa4affd3d8cb90b92595f737467c857f3c8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=1\LUT=2'01 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111111111111111 for cells of type $lut.
Using template $paramod$1b4d85bbf93ebe509b9ca7de00c1b6d509aaa550\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=5\LUT=32'10000000000000000000000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=5\LUT=0 for cells of type $lut.
Using template $paramod\$lut\WIDTH=5\LUT=32'11111111111111111111111111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111111 for cells of type $lut.
No more expansions possible.
<suppressed ~239 debug messages>
2.26. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in top.
Optimizing lut $abc$655$auto$blifparse.cc:498:parse_blif$659.lut1.lut0.lut0 (4 -> 0)
Optimizing lut $abc$655$auto$blifparse.cc:498:parse_blif$666.lut0.lut1 (4 -> 0)
Optimizing lut $abc$655$auto$blifparse.cc:498:parse_blif$659.lut0.lut0.lut0 (4 -> 0)
Optimizing lut $abc$655$auto$blifparse.cc:498:parse_blif$666.lut1.lut0 (4 -> 0)
Optimizing lut $abc$655$auto$blifparse.cc:498:parse_blif$666.lut0.lut0 (4 -> 0)
Optimizing lut $abc$655$auto$blifparse.cc:498:parse_blif$659.lut0.lut0.lut1 (4 -> 0)
Optimizing lut $abc$655$auto$blifparse.cc:498:parse_blif$659.lut0.lut1.lut1 (4 -> 0)
Optimizing lut $abc$655$auto$blifparse.cc:498:parse_blif$659.lut0.lut1.lut0 (4 -> 0)
Optimizing lut $abc$655$auto$blifparse.cc:498:parse_blif$659.lut1.lut0.lut1 (4 -> 0)
Optimizing lut $abc$655$auto$blifparse.cc:498:parse_blif$659.lut1.lut1.lut0 (4 -> 0)
2.27. Executing SETUNDEF pass (replace undef values with defined constants).
2.28. Executing HILOMAP pass (mapping to constant drivers).
2.29. Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).
Marking already mapped port: IBUF.I[0].
Marking already mapped port: OBUF.O[0].
Marking already mapped port: top.clk24_0__io[0].
Marking already mapped port: top.led_0__io[0].
Removed 0 unused cells and 85 unused wires.
2.30. Executing AUTONAME pass.
Renamed 289 objects in module top (14 iterations).
<suppressed ~145 debug messages>
2.31. Executing HIERARCHY pass (managing design hierarchy).
2.31.1. Analyzing design hierarchy..
Top module: \top
2.31.2. Analyzing design hierarchy..
Top module: \top
Removed 0 unused modules.
2.32. Printing statistics.
=== top ===
Number of wires: 158
Number of wire bits: 167
Number of public wires: 158
Number of public wire bits: 167
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 96
ALU 33
DFFE 10
DFFR 7
DFFRE 1
DFFS 17
GND 1
IBUF 1
LUT1 2
LUT3 1
LUT4 11
MUX2_LUT5 6
MUX2_LUT6 3
MUX2_LUT7 1
OBUF 1
VCC 1
2.33. Executing CHECK pass (checking for obvious problems).
checking module top..
found and reported 0 problems.
2.34. Executing Verilog backend.
Dumping module `\top'.
End of script. Logfile hash: 293a8e1109, CPU: user 0.29s system 0.01s, MEM: 28.86 MB peak
Yosys 0.9+3656 (git sha1 dfeff65c, gcc 10.2.0 -march=x86-64 -mtune=generic -O2 -fstack-protector-strong -fno-plt -fPIC -Os)
Time spent: 18% 1x abc (0 sec), 15% 10x read_verilog (0 sec), ...
*** GOWIN Tcl Command Line Console ***
add new file: "top.cst"
add new file: "top.vg"
current device: GW1N-1 GW1N-LV1QN48C6/I5
NOTE (PJ2001) : Skip synthesis, because there is only one netlist file in this project
Reading netlist file: "/home/konrad/dev/fpga-projects/gowin/nmigen/build/top.vg"
ERROR (PA2000) : "/home/konrad/dev/fpga-projects/gowin/nmigen/build/top.vg":1204 | syntax error near token ':'
NOTE (PA0003) : Parsing netlist file "/home/konrad/dev/fpga-projects/gowin/nmigen/build/top.vg" completed with errors
NOTE (PA0005) : Processing netlist completed with errors
Raw
top.debug.v
/* Automatically generated by nMigen 0.3.dev183+g69ed491. Do not edit. */
/* Generated by Yosys 0.9+3656 (git sha1 dfeff65c, gcc 10.2.0 -march=x86-64 -mtune=generic -O2 -fstack-protector-strong -fno-plt -fPIC -Os) */
(* \nmigen.hierarchy = "top.cd_sync" *)
(* generator = "nMigen" *)
module cd_sync(clk, clk24_0__i, rst);
reg \initial = 0;
(* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:218" *)
wire \$1 ;
(* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:218" *)
wire \$3 ;
(* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:221" *)
wire [9:0] \$5 ;
(* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:221" *)
wire [9:0] \$6 ;
(* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:229" *)
wire \$8 ;
(* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:224" *)
output clk;
(* src = "/home/konrad/dev/litex/nmigen/nmigen/build/res.py:143" *)
input clk24_0__i;
(* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:214" *)
wire por_clk;
(* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:216" *)
reg ready = 1'h0;
(* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:216" *)
reg \ready$next ;
(* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:224" *)
output rst;
(* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:215" *)
reg [8:0] timer = 9'h000;
(* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:215" *)
reg [8:0] \timer$next ;
assign \$1 = timer == (* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:218" *) 9'h168;
assign \$3 = timer == (* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:218" *) 9'h168;
assign \$6 = timer + (* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:221" *) 1'h1;
assign \$8 = ~ (* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:229" *) ready;
always @(posedge por_clk)
timer <= \timer$next ;
always @(posedge por_clk)
ready <= \ready$next ;
always @* begin
if (\initial ) begin end
\ready$next = ready;
(* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:218" *)
casez (\$1 )
/* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:218" */
1'h1:
\ready$next = 1'h1;
endcase
end
always @* begin
if (\initial ) begin end
\timer$next = timer;
(* full_case = 32'd1 *)
(* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:218" *)
casez (\$3 )
/* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:218" */
1'h1:
/* empty */;
/* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:220" */
default:
\timer$next = \$5 [8:0];
endcase
end
assign \$5 = \$6 ;
assign rst = \$8 ;
assign clk = clk24_0__i;
assign por_clk = clk24_0__i;
endmodule
(* \nmigen.hierarchy = "top.pin_clk24_0" *)
(* generator = "nMigen" *)
module pin_clk24_0(clk24_0__io, clk24_0__i);
(* src = "/home/konrad/dev/litex/nmigen/nmigen/build/res.py:143" *)
output clk24_0__i;
(* src = "/home/konrad/dev/litex/nmigen/nmigen/build/res.py:129" *)
input clk24_0__io;
IBUF clk24_0_0 (
.I(clk24_0__io),
.O(clk24_0__i)
);
endmodule
(* \nmigen.hierarchy = "top.pin_led_0" *)
(* generator = "nMigen" *)
module pin_led_0(led_0__io, led_0__o);
(* src = "/home/konrad/dev/litex/nmigen/nmigen/build/res.py:129" *)
output led_0__io;
(* src = "/home/konrad/dev/litex/nmigen/nmigen/build/res.py:143" *)
input led_0__o;
OBUF led_0_0 (
.I(led_0__o),
.O(led_0__io)
);
endmodule
(* \nmigen.hierarchy = "top" *)
(* top = 1 *)
(* generator = "nMigen" *)
module top(clk24_0__io, led_0__io);
reg \initial = 0;
(* src = "blinky.py:20" *)
wire \$1 ;
(* src = "blinky.py:24" *)
wire [24:0] \$3 ;
(* src = "blinky.py:24" *)
wire [24:0] \$4 ;
(* src = "blinky.py:20" *)
wire \$6 ;
(* src = "blinky.py:22" *)
wire \$8 ;
(* src = "/home/konrad/dev/litex/nmigen/nmigen/build/res.py:143" *)
wire cd_sync_clk24_0__i;
(* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:224" *)
wire clk;
(* src = "/home/konrad/dev/litex/nmigen/nmigen/build/res.py:129" *)
input clk24_0__io;
(* src = "/home/konrad/dev/litex/nmigen/nmigen/build/res.py:129" *)
output led_0__io;
(* src = "blinky.py:18" *)
reg [23:0] led_counter = 24'hb71aff;
(* src = "blinky.py:18" *)
reg [23:0] \led_counter$next ;
(* src = "/home/konrad/dev/litex/nmigen/nmigen/build/res.py:143" *)
reg pin_led_0_led_0__o = 1'h0;
(* src = "/home/konrad/dev/litex/nmigen/nmigen/build/res.py:143" *)
reg \pin_led_0_led_0__o$next ;
(* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:224" *)
wire rst;
assign \$1 = led_counter == (* src = "blinky.py:20" *) 1'h0;
assign \$4 = led_counter - (* src = "blinky.py:24" *) 1'h1;
assign \$6 = led_counter == (* src = "blinky.py:20" *) 1'h0;
assign \$8 = ~ (* src = "blinky.py:22" *) pin_led_0_led_0__o;
always @(posedge clk)
pin_led_0_led_0__o <= \pin_led_0_led_0__o$next ;
always @(posedge clk)
led_counter <= \led_counter$next ;
cd_sync cd_sync (
.clk(clk),
.clk24_0__i(cd_sync_clk24_0__i),
.rst(rst)
);
pin_clk24_0 pin_clk24_0 (
.clk24_0__i(cd_sync_clk24_0__i),
.clk24_0__io(clk24_0__io)
);
pin_led_0 pin_led_0 (
.led_0__io(led_0__io),
.led_0__o(pin_led_0_led_0__o)
);
always @* begin
if (\initial ) begin end
(* full_case = 32'd1 *)
(* src = "blinky.py:20" *)
casez (\$1 )
/* src = "blinky.py:20" */
1'h1:
\led_counter$next = 24'hb71aff;
/* src = "blinky.py:23" */
default:
\led_counter$next = \$3 [23:0];
endcase
(* src = "/home/konrad/dev/litex/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\led_counter$next = 24'hb71aff;
endcase
end
always @* begin
if (\initial ) begin end
\pin_led_0_led_0__o$next = pin_led_0_led_0__o;
(* src = "blinky.py:20" *)
casez (\$6 )
/* src = "blinky.py:20" */
1'h1:
\pin_led_0_led_0__o$next = \$8 ;
endcase
(* src = "/home/konrad/dev/litex/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\pin_led_0_led_0__o$next = 1'h0;
endcase
end
assign \$3 = \$4 ;
endmodule
Raw
top.vg
/* Generated by Yosys 0.9+3656 (git sha1 dfeff65c, gcc 10.2.0 -march=x86-64 -mtune=generic -O2 -fstack-protector-strong -fno-plt -fPIC -Os) */
/* top = 1 */
/* src = "top.v:70.1-134.10" */
module top(clk24_0__io, led_0__io);
wire \$3[0] ;
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \$3[0]_ALU_SUM_COUT ;
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:165.41-165.66|/usr/bin/../share/yosys/gowin/cells_map.v:159.41-159.66|/usr/bin/../share/yosys/gowin/cells_map.v:152.9-152.11" */
wire \$3[0]_ALU_SUM_I1 ;
wire \$3[10] ;
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \$3[10]_ALU_SUM_COUT ;
wire \$3[11] ;
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \$3[11]_ALU_SUM_COUT ;
wire \$3[12] ;
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \$3[12]_ALU_SUM_COUT ;
wire \$3[13] ;
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \$3[13]_ALU_SUM_COUT ;
wire \$3[14] ;
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \$3[14]_ALU_SUM_COUT ;
wire \$3[15] ;
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \$3[15]_ALU_SUM_COUT ;
wire \$3[16] ;
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \$3[16]_ALU_SUM_COUT ;
wire \$3[17] ;
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \$3[17]_ALU_SUM_COUT ;
wire \$3[18] ;
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \$3[18]_ALU_SUM_COUT ;
wire \$3[19] ;
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \$3[19]_ALU_SUM_COUT ;
wire \$3[1] ;
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \$3[1]_ALU_SUM_COUT ;
wire \$3[20] ;
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \$3[20]_ALU_SUM_COUT ;
wire \$3[21] ;
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \$3[21]_ALU_SUM_COUT ;
wire \$3[22] ;
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \$3[22]_ALU_SUM_COUT ;
wire \$3[23] ;
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
/* unused_bits = "0" */
wire \$3[23]_ALU_SUM_COUT ;
wire \$3[2] ;
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \$3[2]_ALU_SUM_COUT ;
wire \$3[3] ;
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \$3[3]_ALU_SUM_COUT ;
wire \$3[4] ;
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \$3[4]_ALU_SUM_COUT ;
wire \$3[5] ;
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \$3[5]_ALU_SUM_COUT ;
wire \$3[6] ;
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \$3[6]_ALU_SUM_COUT ;
wire \$3[7] ;
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \$3[7]_ALU_SUM_COUT ;
wire \$3[8] ;
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \$3[8]_ALU_SUM_COUT ;
wire \$3[9] ;
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \$3[9]_ALU_SUM_COUT ;
/* src = "top.v:74.15-74.18" */
wire \$4[0] ;
/* src = "top.v:74.15-74.18" */
wire \$4[10] ;
/* src = "top.v:74.15-74.18" */
wire \$4[11] ;
/* src = "top.v:74.15-74.18" */
wire \$4[12] ;
/* src = "top.v:74.15-74.18" */
wire \$4[13] ;
/* src = "top.v:74.15-74.18" */
wire \$4[14] ;
/* src = "top.v:74.15-74.18" */
wire \$4[15] ;
/* src = "top.v:74.15-74.18" */
wire \$4[16] ;
/* src = "top.v:74.15-74.18" */
wire \$4[17] ;
/* src = "top.v:74.15-74.18" */
wire \$4[18] ;
/* src = "top.v:74.15-74.18" */
wire \$4[19] ;
/* src = "top.v:74.15-74.18" */
wire \$4[1] ;
/* src = "top.v:74.15-74.18" */
wire \$4[20] ;
/* src = "top.v:74.15-74.18" */
wire \$4[21] ;
/* src = "top.v:74.15-74.18" */
wire \$4[22] ;
/* src = "top.v:74.15-74.18" */
wire \$4[23] ;
/* src = "top.v:74.15-74.18" */
wire \$4[24] ;
/* src = "top.v:74.15-74.18" */
wire \$4[2] ;
/* src = "top.v:74.15-74.18" */
wire \$4[3] ;
/* src = "top.v:74.15-74.18" */
wire \$4[4] ;
/* src = "top.v:74.15-74.18" */
wire \$4[5] ;
/* src = "top.v:74.15-74.18" */
wire \$4[6] ;
/* src = "top.v:74.15-74.18" */
wire \$4[7] ;
/* src = "top.v:74.15-74.18" */
wire \$4[8] ;
/* src = "top.v:74.15-74.18" */
wire \$4[9] ;
/* src = "top.v:76.8-76.11" */
wire \$8 ;
/* hdlname = "cd_sync $5" */
/* src = "top.v:94.11-98.4|top.v:8.14-8.17" */
wire \cd_sync.$5[0] ;
/* src = "top.v:94.11-98.4|top.v:21.17-21.29|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \cd_sync.$5[0]_ALU_SUM_COUT ;
/* hdlname = "cd_sync $5" */
/* src = "top.v:94.11-98.4|top.v:8.14-8.17" */
wire \cd_sync.$5[1] ;
/* src = "top.v:94.11-98.4|top.v:21.17-21.29|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \cd_sync.$5[1]_ALU_SUM_COUT ;
/* hdlname = "cd_sync $5" */
/* src = "top.v:94.11-98.4|top.v:8.14-8.17" */
wire \cd_sync.$5[2] ;
/* src = "top.v:94.11-98.4|top.v:21.17-21.29|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \cd_sync.$5[2]_ALU_SUM_COUT ;
/* hdlname = "cd_sync $5" */
/* src = "top.v:94.11-98.4|top.v:8.14-8.17" */
wire \cd_sync.$5[3] ;
/* src = "top.v:94.11-98.4|top.v:21.17-21.29|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \cd_sync.$5[3]_ALU_SUM_COUT ;
/* hdlname = "cd_sync $5" */
/* src = "top.v:94.11-98.4|top.v:8.14-8.17" */
wire \cd_sync.$5[4] ;
/* src = "top.v:94.11-98.4|top.v:21.17-21.29|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \cd_sync.$5[4]_ALU_SUM_COUT ;
/* hdlname = "cd_sync $5" */
/* src = "top.v:94.11-98.4|top.v:8.14-8.17" */
wire \cd_sync.$5[5] ;
/* src = "top.v:94.11-98.4|top.v:21.17-21.29|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \cd_sync.$5[5]_ALU_SUM_COUT ;
/* hdlname = "cd_sync $5" */
/* src = "top.v:94.11-98.4|top.v:8.14-8.17" */
wire \cd_sync.$5[6] ;
/* src = "top.v:94.11-98.4|top.v:21.17-21.29|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \cd_sync.$5[6]_ALU_SUM_COUT ;
/* hdlname = "cd_sync $5" */
/* src = "top.v:94.11-98.4|top.v:8.14-8.17" */
wire \cd_sync.$5[7] ;
/* src = "top.v:94.11-98.4|top.v:21.17-21.29|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
wire \cd_sync.$5[7]_ALU_SUM_COUT ;
/* hdlname = "cd_sync $5" */
/* src = "top.v:94.11-98.4|top.v:8.14-8.17" */
wire \cd_sync.$5[8] ;
/* src = "top.v:94.11-98.4|top.v:21.17-21.29|/usr/bin/../share/yosys/gowin/arith_map.v:38.25-38.27" */
/* unused_bits = "0" */
wire \cd_sync.$5[8]_ALU_SUM_COUT ;
/* hdlname = "cd_sync clk" */
/* src = "top.v:94.11-98.4|top.v:11.10-11.13" */
wire \cd_sync.clk ;
/* hdlname = "cd_sync clk24_0__i" */
/* src = "top.v:94.11-98.4|top.v:12.9-12.19" */
wire \cd_sync.clk24_0__i ;
/* hdlname = "cd_sync initial" */
/* src = "top.v:94.11-98.4|top.v:5.7-5.15" */
wire \cd_sync.initial ;
/* hdlname = "cd_sync por_clk" */
/* src = "top.v:94.11-98.4|top.v:13.8-13.15" */
wire \cd_sync.por_clk ;
/* hdlname = "cd_sync ready" */
/* src = "top.v:94.11-98.4|top.v:14.7-14.12" */
wire \cd_sync.ready ;
wire \cd_sync.ready_DFFE_Q_CE ;
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:164.9-164.11" */
wire \cd_sync.ready_MUX2_LUT7_S0_I0 ;
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:165.41-165.66|/usr/bin/../share/yosys/gowin/cells_map.v:158.9-158.11" */
wire \cd_sync.ready_MUX2_LUT7_S0_I0_MUX2_LUT6_O_I0 ;
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:165.41-165.66|/usr/bin/../share/yosys/gowin/cells_map.v:158.13-158.15" */
wire \cd_sync.ready_MUX2_LUT7_S0_I0_MUX2_LUT6_O_I1 ;
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:164.13-164.15" */
wire \cd_sync.ready_MUX2_LUT7_S0_I1 ;
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:166.42-166.67|/usr/bin/../share/yosys/gowin/cells_map.v:158.9-158.11" */
wire \cd_sync.ready_MUX2_LUT7_S0_I1_MUX2_LUT6_O_I0 ;
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:166.42-166.67|/usr/bin/../share/yosys/gowin/cells_map.v:158.13-158.15" */
wire \cd_sync.ready_MUX2_LUT7_S0_I1_MUX2_LUT6_O_I1 ;
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:166.42-166.67|/usr/bin/../share/yosys/gowin/cells_map.v:160.41-160.66|/usr/bin/../share/yosys/gowin/cells_map.v:152.13-152.15" */
wire \cd_sync.ready_MUX2_LUT7_S0_I1_MUX2_LUT6_O_I1_MUX2_LUT5_O_I1 ;
wire \cd_sync.ready_MUX2_LUT7_S0_O ;
/* hdlname = "cd_sync timer" */
/* src = "top.v:94.11-98.4|top.v:17.13-17.18" */
wire \cd_sync.timer[0] ;
/* hdlname = "cd_sync timer" */
/* src = "top.v:94.11-98.4|top.v:17.13-17.18" */
wire \cd_sync.timer[1] ;
/* hdlname = "cd_sync timer" */
/* src = "top.v:94.11-98.4|top.v:17.13-17.18" */
wire \cd_sync.timer[2] ;
/* force_downto = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:131.20-131.21" */
wire [3:0] \cd_sync.timer[2]_LUT3_I0_F ;
/* hdlname = "cd_sync timer" */
/* src = "top.v:94.11-98.4|top.v:17.13-17.18" */
wire \cd_sync.timer[3] ;
/* hdlname = "cd_sync timer" */
/* src = "top.v:94.11-98.4|top.v:17.13-17.18" */
wire \cd_sync.timer[4] ;
/* hdlname = "cd_sync timer" */
/* src = "top.v:94.11-98.4|top.v:17.13-17.18" */
wire \cd_sync.timer[5] ;
wire \cd_sync.timer[5]_LUT4_I2_1_F ;
/* hdlname = "cd_sync timer" */
/* src = "top.v:94.11-98.4|top.v:17.13-17.18" */
wire \cd_sync.timer[6] ;
/* hdlname = "cd_sync timer" */
/* src = "top.v:94.11-98.4|top.v:17.13-17.18" */
wire \cd_sync.timer[7] ;
/* hdlname = "cd_sync timer" */
/* src = "top.v:94.11-98.4|top.v:17.13-17.18" */
wire \cd_sync.timer[8] ;
/* src = "top.v:77.8-77.26" */
wire cd_sync_clk24_0__i;
/* src = "top.v:78.8-78.11" */
wire clk;
/* src = "top.v:79.9-79.20" */
input clk24_0__io;
/* src = "top.v:71.7-71.15" */
wire \initial ;
/* src = "top.v:80.10-80.19" */
output led_0__io;
/* src = "top.v:81.14-81.25" */
wire \led_counter[0] ;
/* src = "top.v:81.14-81.25" */
wire \led_counter[10] ;
/* src = "top.v:81.14-81.25" */
wire \led_counter[11] ;
/* src = "top.v:81.14-81.25" */
wire \led_counter[12] ;
/* src = "top.v:81.14-81.25" */
wire \led_counter[13] ;
/* src = "top.v:81.14-81.25" */
wire \led_counter[14] ;
/* src = "top.v:81.14-81.25" */
wire \led_counter[15] ;
/* src = "top.v:81.14-81.25" */
wire \led_counter[16] ;
/* src = "top.v:81.14-81.25" */
wire \led_counter[17] ;
/* src = "top.v:81.14-81.25" */
wire \led_counter[18] ;
/* src = "top.v:81.14-81.25" */
wire \led_counter[19] ;
/* src = "top.v:81.14-81.25" */
wire \led_counter[1] ;
/* src = "top.v:81.14-81.25" */
wire \led_counter[20] ;
/* src = "top.v:81.14-81.25" */
wire \led_counter[21] ;
/* src = "top.v:81.14-81.25" */
wire \led_counter[22] ;
/* src = "top.v:81.14-81.25" */
wire \led_counter[23] ;
/* src = "top.v:81.14-81.25" */
wire \led_counter[2] ;
/* src = "top.v:81.14-81.25" */
wire \led_counter[3] ;
/* src = "top.v:81.14-81.25" */
wire \led_counter[4] ;
/* force_downto = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:131.20-131.21" */
wire [6:0] \led_counter[4]_LUT4_I0_F ;
/* src = "top.v:81.14-81.25" */
wire \led_counter[5] ;
/* src = "top.v:81.14-81.25" */
wire \led_counter[6] ;
/* src = "top.v:81.14-81.25" */
wire \led_counter[7] ;
/* src = "top.v:81.14-81.25" */
wire \led_counter[8] ;
/* src = "top.v:81.14-81.25" */
wire \led_counter[9] ;
/* hdlname = "pin_clk24_0 clk24_0__i" */
/* src = "top.v:99.15-102.4|top.v:53.10-53.20" */
wire \pin_clk24_0.clk24_0__i ;
/* hdlname = "pin_clk24_0 clk24_0__io" */
/* src = "top.v:99.15-102.4|top.v:54.9-54.20" */
wire \pin_clk24_0.clk24_0__io ;
/* hdlname = "pin_led_0 led_0__io" */
/* src = "top.v:103.13-106.4|top.v:62.10-62.19" */
wire \pin_led_0.led_0__io ;
/* hdlname = "pin_led_0 led_0__o" */
/* src = "top.v:103.13-106.4|top.v:63.9-63.17" */
wire \pin_led_0.led_0__o ;
/* src = "top.v:83.7-83.25" */
wire pin_led_0_led_0__o;
wire pin_led_0_led_0__o_DFFRE_Q_CE;
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:158.9-158.11" */
wire pin_led_0_led_0__o_DFFRE_Q_CE_MUX2_LUT6_O_I0;
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:158.13-158.15" */
wire pin_led_0_led_0__o_DFFRE_Q_CE_MUX2_LUT6_O_I1;
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:160.41-160.66|/usr/bin/../share/yosys/gowin/cells_map.v:152.13-152.15" */
wire pin_led_0_led_0__o_DFFRE_Q_CE_MUX2_LUT6_O_I1_MUX2_LUT5_O_I1;
wire pin_led_0_led_0__o_DFFRE_Q_RESET;
/* module_not_derived = 1 */
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \$3[0]_ALU_SUM (
.CIN(\$3[0]_ALU_SUM_I1 ),
.COUT(\$3[0]_ALU_SUM_COUT ),
.I0(\led_counter[0] ),
.I1(\$3[0]_ALU_SUM_I1 ),
.I3(\cd_sync.initial ),
.SUM(\$3[0] )
);
defparam \$3[0]_ALU_SUM .ALU_MODE = 2;
VCC \$3[0]_ALU_SUM_I1_VCC_V (
.V(\$3[0]_ALU_SUM_I1 )
);
/* module_not_derived = 1 */
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \$3[10]_ALU_SUM (
.CIN(\$3[9]_ALU_SUM_COUT ),
.COUT(\$3[10]_ALU_SUM_COUT ),
.I0(\led_counter[10] ),
.I1(\cd_sync.initial ),
.I3(\cd_sync.initial ),
.SUM(\$3[10] )
);
defparam \$3[10]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \$3[11]_ALU_SUM (
.CIN(\$3[10]_ALU_SUM_COUT ),
.COUT(\$3[11]_ALU_SUM_COUT ),
.I0(\led_counter[11] ),
.I1(\cd_sync.initial ),
.I3(\cd_sync.initial ),
.SUM(\$3[11] )
);
defparam \$3[11]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \$3[12]_ALU_SUM (
.CIN(\$3[11]_ALU_SUM_COUT ),
.COUT(\$3[12]_ALU_SUM_COUT ),
.I0(\led_counter[12] ),
.I1(\cd_sync.initial ),
.I3(\cd_sync.initial ),
.SUM(\$3[12] )
);
defparam \$3[12]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \$3[13]_ALU_SUM (
.CIN(\$3[12]_ALU_SUM_COUT ),
.COUT(\$3[13]_ALU_SUM_COUT ),
.I0(\led_counter[13] ),
.I1(\cd_sync.initial ),
.I3(\cd_sync.initial ),
.SUM(\$3[13] )
);
defparam \$3[13]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \$3[14]_ALU_SUM (
.CIN(\$3[13]_ALU_SUM_COUT ),
.COUT(\$3[14]_ALU_SUM_COUT ),
.I0(\led_counter[14] ),
.I1(\cd_sync.initial ),
.I3(\cd_sync.initial ),
.SUM(\$3[14] )
);
defparam \$3[14]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \$3[15]_ALU_SUM (
.CIN(\$3[14]_ALU_SUM_COUT ),
.COUT(\$3[15]_ALU_SUM_COUT ),
.I0(\led_counter[15] ),
.I1(\cd_sync.initial ),
.I3(\cd_sync.initial ),
.SUM(\$3[15] )
);
defparam \$3[15]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \$3[16]_ALU_SUM (
.CIN(\$3[15]_ALU_SUM_COUT ),
.COUT(\$3[16]_ALU_SUM_COUT ),
.I0(\led_counter[16] ),
.I1(\cd_sync.initial ),
.I3(\cd_sync.initial ),
.SUM(\$3[16] )
);
defparam \$3[16]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \$3[17]_ALU_SUM (
.CIN(\$3[16]_ALU_SUM_COUT ),
.COUT(\$3[17]_ALU_SUM_COUT ),
.I0(\led_counter[17] ),
.I1(\cd_sync.initial ),
.I3(\cd_sync.initial ),
.SUM(\$3[17] )
);
defparam \$3[17]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \$3[18]_ALU_SUM (
.CIN(\$3[17]_ALU_SUM_COUT ),
.COUT(\$3[18]_ALU_SUM_COUT ),
.I0(\led_counter[18] ),
.I1(\cd_sync.initial ),
.I3(\cd_sync.initial ),
.SUM(\$3[18] )
);
defparam \$3[18]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \$3[19]_ALU_SUM (
.CIN(\$3[18]_ALU_SUM_COUT ),
.COUT(\$3[19]_ALU_SUM_COUT ),
.I0(\led_counter[19] ),
.I1(\cd_sync.initial ),
.I3(\cd_sync.initial ),
.SUM(\$3[19] )
);
defparam \$3[19]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \$3[1]_ALU_SUM (
.CIN(\$3[0]_ALU_SUM_COUT ),
.COUT(\$3[1]_ALU_SUM_COUT ),
.I0(\led_counter[1] ),
.I1(\cd_sync.initial ),
.I3(\cd_sync.initial ),
.SUM(\$3[1] )
);
defparam \$3[1]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \$3[20]_ALU_SUM (
.CIN(\$3[19]_ALU_SUM_COUT ),
.COUT(\$3[20]_ALU_SUM_COUT ),
.I0(\led_counter[20] ),
.I1(\cd_sync.initial ),
.I3(\cd_sync.initial ),
.SUM(\$3[20] )
);
defparam \$3[20]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \$3[21]_ALU_SUM (
.CIN(\$3[20]_ALU_SUM_COUT ),
.COUT(\$3[21]_ALU_SUM_COUT ),
.I0(\led_counter[21] ),
.I1(\cd_sync.initial ),
.I3(\cd_sync.initial ),
.SUM(\$3[21] )
);
defparam \$3[21]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \$3[22]_ALU_SUM (
.CIN(\$3[21]_ALU_SUM_COUT ),
.COUT(\$3[22]_ALU_SUM_COUT ),
.I0(\led_counter[22] ),
.I1(\cd_sync.initial ),
.I3(\cd_sync.initial ),
.SUM(\$3[22] )
);
defparam \$3[22]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \$3[23]_ALU_SUM (
.CIN(\$3[22]_ALU_SUM_COUT ),
.COUT(\$3[23]_ALU_SUM_COUT ),
.I0(\led_counter[23] ),
.I1(\cd_sync.initial ),
.I3(\cd_sync.initial ),
.SUM(\$3[23] )
);
defparam \$3[23]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \$3[2]_ALU_SUM (
.CIN(\$3[1]_ALU_SUM_COUT ),
.COUT(\$3[2]_ALU_SUM_COUT ),
.I0(\led_counter[2] ),
.I1(\cd_sync.initial ),
.I3(\cd_sync.initial ),
.SUM(\$3[2] )
);
defparam \$3[2]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \$3[3]_ALU_SUM (
.CIN(\$3[2]_ALU_SUM_COUT ),
.COUT(\$3[3]_ALU_SUM_COUT ),
.I0(\led_counter[3] ),
.I1(\cd_sync.initial ),
.I3(\cd_sync.initial ),
.SUM(\$3[3] )
);
defparam \$3[3]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \$3[4]_ALU_SUM (
.CIN(\$3[3]_ALU_SUM_COUT ),
.COUT(\$3[4]_ALU_SUM_COUT ),
.I0(\led_counter[4] ),
.I1(\cd_sync.initial ),
.I3(\cd_sync.initial ),
.SUM(\$3[4] )
);
defparam \$3[4]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \$3[5]_ALU_SUM (
.CIN(\$3[4]_ALU_SUM_COUT ),
.COUT(\$3[5]_ALU_SUM_COUT ),
.I0(\led_counter[5] ),
.I1(\cd_sync.initial ),
.I3(\cd_sync.initial ),
.SUM(\$3[5] )
);
defparam \$3[5]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \$3[6]_ALU_SUM (
.CIN(\$3[5]_ALU_SUM_COUT ),
.COUT(\$3[6]_ALU_SUM_COUT ),
.I0(\led_counter[6] ),
.I1(\cd_sync.initial ),
.I3(\cd_sync.initial ),
.SUM(\$3[6] )
);
defparam \$3[6]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \$3[7]_ALU_SUM (
.CIN(\$3[6]_ALU_SUM_COUT ),
.COUT(\$3[7]_ALU_SUM_COUT ),
.I0(\led_counter[7] ),
.I1(\cd_sync.initial ),
.I3(\cd_sync.initial ),
.SUM(\$3[7] )
);
defparam \$3[7]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \$3[8]_ALU_SUM (
.CIN(\$3[7]_ALU_SUM_COUT ),
.COUT(\$3[8]_ALU_SUM_COUT ),
.I0(\led_counter[8] ),
.I1(\cd_sync.initial ),
.I3(\cd_sync.initial ),
.SUM(\$3[8] )
);
defparam \$3[8]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:87.17-87.35|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \$3[9]_ALU_SUM (
.CIN(\$3[8]_ALU_SUM_COUT ),
.COUT(\$3[9]_ALU_SUM_COUT ),
.I0(\led_counter[9] ),
.I1(\cd_sync.initial ),
.I3(\cd_sync.initial ),
.SUM(\$3[9] )
);
defparam \$3[9]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:136.23-137.15" */
LUT1 \$8_LUT1_F (
.F(\$8 ),
.I0(pin_led_0_led_0__o)
);
defparam \$8_LUT1_F .INIT = 2'h1;
/* module_not_derived = 1 */
/* src = "top.v:94.11-98.4|top.v:21.17-21.29|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \cd_sync.$5[0]_ALU_SUM (
.CIN(\cd_sync.initial ),
.COUT(\cd_sync.$5[0]_ALU_SUM_COUT ),
.I0(\$3[0]_ALU_SUM_I1 ),
.I1(\cd_sync.timer[0] ),
.I3(\$3[0]_ALU_SUM_I1 ),
.SUM(\cd_sync.$5[0] )
);
defparam \cd_sync.$5[0]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:94.11-98.4|top.v:21.17-21.29|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \cd_sync.$5[1]_ALU_SUM (
.CIN(\cd_sync.$5[0]_ALU_SUM_COUT ),
.COUT(\cd_sync.$5[1]_ALU_SUM_COUT ),
.I0(\cd_sync.initial ),
.I1(\cd_sync.timer[1] ),
.I3(\$3[0]_ALU_SUM_I1 ),
.SUM(\cd_sync.$5[1] )
);
defparam \cd_sync.$5[1]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:94.11-98.4|top.v:21.17-21.29|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \cd_sync.$5[2]_ALU_SUM (
.CIN(\cd_sync.$5[1]_ALU_SUM_COUT ),
.COUT(\cd_sync.$5[2]_ALU_SUM_COUT ),
.I0(\cd_sync.initial ),
.I1(\cd_sync.timer[2] ),
.I3(\$3[0]_ALU_SUM_I1 ),
.SUM(\cd_sync.$5[2] )
);
defparam \cd_sync.$5[2]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:94.11-98.4|top.v:21.17-21.29|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \cd_sync.$5[3]_ALU_SUM (
.CIN(\cd_sync.$5[2]_ALU_SUM_COUT ),
.COUT(\cd_sync.$5[3]_ALU_SUM_COUT ),
.I0(\cd_sync.initial ),
.I1(\cd_sync.timer[3] ),
.I3(\$3[0]_ALU_SUM_I1 ),
.SUM(\cd_sync.$5[3] )
);
defparam \cd_sync.$5[3]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:94.11-98.4|top.v:21.17-21.29|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \cd_sync.$5[4]_ALU_SUM (
.CIN(\cd_sync.$5[3]_ALU_SUM_COUT ),
.COUT(\cd_sync.$5[4]_ALU_SUM_COUT ),
.I0(\cd_sync.initial ),
.I1(\cd_sync.timer[4] ),
.I3(\$3[0]_ALU_SUM_I1 ),
.SUM(\cd_sync.$5[4] )
);
defparam \cd_sync.$5[4]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:94.11-98.4|top.v:21.17-21.29|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \cd_sync.$5[5]_ALU_SUM (
.CIN(\cd_sync.$5[4]_ALU_SUM_COUT ),
.COUT(\cd_sync.$5[5]_ALU_SUM_COUT ),
.I0(\cd_sync.initial ),
.I1(\cd_sync.timer[5] ),
.I3(\$3[0]_ALU_SUM_I1 ),
.SUM(\cd_sync.$5[5] )
);
defparam \cd_sync.$5[5]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:94.11-98.4|top.v:21.17-21.29|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \cd_sync.$5[6]_ALU_SUM (
.CIN(\cd_sync.$5[5]_ALU_SUM_COUT ),
.COUT(\cd_sync.$5[6]_ALU_SUM_COUT ),
.I0(\cd_sync.initial ),
.I1(\cd_sync.timer[6] ),
.I3(\$3[0]_ALU_SUM_I1 ),
.SUM(\cd_sync.$5[6] )
);
defparam \cd_sync.$5[6]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:94.11-98.4|top.v:21.17-21.29|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \cd_sync.$5[7]_ALU_SUM (
.CIN(\cd_sync.$5[6]_ALU_SUM_COUT ),
.COUT(\cd_sync.$5[7]_ALU_SUM_COUT ),
.I0(\cd_sync.initial ),
.I1(\cd_sync.timer[7] ),
.I3(\$3[0]_ALU_SUM_I1 ),
.SUM(\cd_sync.$5[7] )
);
defparam \cd_sync.$5[7]_ALU_SUM .ALU_MODE = 2;
/* module_not_derived = 1 */
/* src = "top.v:94.11-98.4|top.v:21.17-21.29|/usr/bin/../share/yosys/gowin/arith_map.v:57.7-63.5" */
ALU \cd_sync.$5[8]_ALU_SUM (
.CIN(\cd_sync.$5[7]_ALU_SUM_COUT ),
.COUT(\cd_sync.$5[8]_ALU_SUM_COUT ),
.I0(\cd_sync.initial ),
.I1(\cd_sync.timer[8] ),
.I3(\$3[0]_ALU_SUM_I1 ),
.SUM(\cd_sync.$5[8] )
);
defparam \cd_sync.$5[8]_ALU_SUM .ALU_MODE = 2;
GND \cd_sync.initial_GND_G (
.G(\cd_sync.initial )
);
/* module_not_derived = 1 */
/* src = "top.v:94.11-98.4|top.v:25.3-26.27|/usr/bin/../share/yosys/gowin/cells_map.v:19.7-19.56" */
DFFE \cd_sync.ready_DFFE_Q (
.CE(\cd_sync.ready_DFFE_Q_CE ),
.CLK(\cd_sync.por_clk ),
.D(\$3[0]_ALU_SUM_I1 ),
.Q(\cd_sync.ready )
);
/* module_not_derived = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:136.23-137.15" */
LUT1 \cd_sync.ready_LUT1_I0 (
.F(pin_led_0_led_0__o_DFFRE_Q_RESET),
.I0(\cd_sync.ready )
);
defparam \cd_sync.ready_LUT1_I0 .INIT = 2'h1;
/* module_not_derived = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:167.14-167.54" */
MUX2_LUT7 \cd_sync.ready_MUX2_LUT7_S0 (
.I0(\cd_sync.ready_MUX2_LUT7_S0_I0 ),
.I1(\cd_sync.ready_MUX2_LUT7_S0_I1 ),
.O(\cd_sync.ready_MUX2_LUT7_S0_O ),
.S0(\cd_sync.ready )
);
/* module_not_derived = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:165.41-165.66|/usr/bin/../share/yosys/gowin/cells_map.v:161.14-161.54" */
MUX2_LUT6 \cd_sync.ready_MUX2_LUT7_S0_I0_MUX2_LUT6_O (
.I0(\cd_sync.ready_MUX2_LUT7_S0_I0_MUX2_LUT6_O_I0 ),
.I1(\cd_sync.ready_MUX2_LUT7_S0_I0_MUX2_LUT6_O_I1 ),
.O(\cd_sync.ready_MUX2_LUT7_S0_I0 ),
.S0(\led_counter[4]_LUT4_I0_F [5])
);
/* module_not_derived = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:165.41-165.66|/usr/bin/../share/yosys/gowin/cells_map.v:159.41-159.66|/usr/bin/../share/yosys/gowin/cells_map.v:155.14-155.54" */
MUX2_LUT5 \cd_sync.ready_MUX2_LUT7_S0_I0_MUX2_LUT6_O_I0_MUX2_LUT5_O (
.I0(\$3[0]_ALU_SUM_I1 ),
.I1(\$3[0]_ALU_SUM_I1 ),
.O(\cd_sync.ready_MUX2_LUT7_S0_I0_MUX2_LUT6_O_I0 ),
.S0(\led_counter[4]_LUT4_I0_F [4])
);
/* module_not_derived = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:165.41-165.66|/usr/bin/../share/yosys/gowin/cells_map.v:160.41-160.66|/usr/bin/../share/yosys/gowin/cells_map.v:155.14-155.54" */
MUX2_LUT5 \cd_sync.ready_MUX2_LUT7_S0_I0_MUX2_LUT6_O_I1_MUX2_LUT5_O (
.I0(\$3[0]_ALU_SUM_I1 ),
.I1(\$3[0]_ALU_SUM_I1 ),
.O(\cd_sync.ready_MUX2_LUT7_S0_I0_MUX2_LUT6_O_I1 ),
.S0(\led_counter[4]_LUT4_I0_F [4])
);
/* module_not_derived = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:166.42-166.67|/usr/bin/../share/yosys/gowin/cells_map.v:161.14-161.54" */
MUX2_LUT6 \cd_sync.ready_MUX2_LUT7_S0_I1_MUX2_LUT6_O (
.I0(\cd_sync.ready_MUX2_LUT7_S0_I1_MUX2_LUT6_O_I0 ),
.I1(\cd_sync.ready_MUX2_LUT7_S0_I1_MUX2_LUT6_O_I1 ),
.O(\cd_sync.ready_MUX2_LUT7_S0_I1 ),
.S0(\led_counter[4]_LUT4_I0_F [5])
);
/* module_not_derived = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:166.42-166.67|/usr/bin/../share/yosys/gowin/cells_map.v:159.41-159.66|/usr/bin/../share/yosys/gowin/cells_map.v:155.14-155.54" */
MUX2_LUT5 \cd_sync.ready_MUX2_LUT7_S0_I1_MUX2_LUT6_O_I0_MUX2_LUT5_O (
.I0(\cd_sync.initial ),
.I1(\cd_sync.initial ),
.O(\cd_sync.ready_MUX2_LUT7_S0_I1_MUX2_LUT6_O_I0 ),
.S0(\led_counter[4]_LUT4_I0_F [4])
);
/* module_not_derived = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:166.42-166.67|/usr/bin/../share/yosys/gowin/cells_map.v:160.41-160.66|/usr/bin/../share/yosys/gowin/cells_map.v:155.14-155.54" */
MUX2_LUT5 \cd_sync.ready_MUX2_LUT7_S0_I1_MUX2_LUT6_O_I1_MUX2_LUT5_O (
.I0(\cd_sync.initial ),
.I1(\cd_sync.ready_MUX2_LUT7_S0_I1_MUX2_LUT6_O_I1_MUX2_LUT5_O_I1 ),
.O(\cd_sync.ready_MUX2_LUT7_S0_I1_MUX2_LUT6_O_I1 ),
.S0(\led_counter[4]_LUT4_I0_F [4])
);
/* module_not_derived = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:166.42-166.67|/usr/bin/../share/yosys/gowin/cells_map.v:160.41-160.66|/usr/bin/../share/yosys/gowin/cells_map.v:154.41-154.66|/usr/bin/../share/yosys/gowin/cells_map.v:148.23-149.48" */
LUT4 \cd_sync.ready_MUX2_LUT7_S0_I1_MUX2_LUT6_O_I1_MUX2_LUT5_O_I1_LUT4_F (
.F(\cd_sync.ready_MUX2_LUT7_S0_I1_MUX2_LUT6_O_I1_MUX2_LUT5_O_I1 ),
.I0(\led_counter[4]_LUT4_I0_F [0]),
.I1(\led_counter[4]_LUT4_I0_F [1]),
.I2(\led_counter[4]_LUT4_I0_F [2]),
.I3(\led_counter[4]_LUT4_I0_F [3])
);
defparam \cd_sync.ready_MUX2_LUT7_S0_I1_MUX2_LUT6_O_I1_MUX2_LUT5_O_I1_LUT4_F .INIT = 16'h8000;
/* module_not_derived = 1 */
/* src = "top.v:94.11-98.4|top.v:23.3-24.27|/usr/bin/../share/yosys/gowin/cells_map.v:19.7-19.56" */
DFFE \cd_sync.timer[0]_DFFE_Q (
.CE(\cd_sync.timer[5]_LUT4_I2_1_F ),
.CLK(\cd_sync.por_clk ),
.D(\cd_sync.$5[0] ),
.Q(\cd_sync.timer[0] )
);
/* module_not_derived = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:148.23-149.48" */
LUT4 \cd_sync.timer[0]_LUT4_I0 (
.F(\cd_sync.timer[2]_LUT3_I0_F [1]),
.I0(\cd_sync.timer[0] ),
.I1(\cd_sync.timer[1] ),
.I2(\cd_sync.timer[6] ),
.I3(\cd_sync.timer[8] )
);
defparam \cd_sync.timer[0]_LUT4_I0 .INIT = 16'h1000;
/* module_not_derived = 1 */
/* src = "top.v:94.11-98.4|top.v:23.3-24.27|/usr/bin/../share/yosys/gowin/cells_map.v:19.7-19.56" */
DFFE \cd_sync.timer[1]_DFFE_Q (
.CE(\cd_sync.timer[5]_LUT4_I2_1_F ),
.CLK(\cd_sync.por_clk ),
.D(\cd_sync.$5[1] ),
.Q(\cd_sync.timer[1] )
);
/* module_not_derived = 1 */
/* src = "top.v:94.11-98.4|top.v:23.3-24.27|/usr/bin/../share/yosys/gowin/cells_map.v:19.7-19.56" */
DFFE \cd_sync.timer[2]_DFFE_Q (
.CE(\cd_sync.timer[5]_LUT4_I2_1_F ),
.CLK(\cd_sync.por_clk ),
.D(\cd_sync.$5[2] ),
.Q(\cd_sync.timer[2] )
);
/* module_not_derived = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:144.23-145.37" */
LUT3 \cd_sync.timer[2]_LUT3_I0 (
.F(\cd_sync.timer[2]_LUT3_I0_F [0]),
.I0(\cd_sync.timer[2] ),
.I1(\cd_sync.timer[4] ),
.I2(\cd_sync.timer[7] )
);
defparam \cd_sync.timer[2]_LUT3_I0 .INIT = 8'h01;
/* module_not_derived = 1 */
/* src = "top.v:94.11-98.4|top.v:23.3-24.27|/usr/bin/../share/yosys/gowin/cells_map.v:19.7-19.56" */
DFFE \cd_sync.timer[3]_DFFE_Q (
.CE(\cd_sync.timer[5]_LUT4_I2_1_F ),
.CLK(\cd_sync.por_clk ),
.D(\cd_sync.$5[3] ),
.Q(\cd_sync.timer[3] )
);
/* module_not_derived = 1 */
/* src = "top.v:94.11-98.4|top.v:23.3-24.27|/usr/bin/../share/yosys/gowin/cells_map.v:19.7-19.56" */
DFFE \cd_sync.timer[4]_DFFE_Q (
.CE(\cd_sync.timer[5]_LUT4_I2_1_F ),
.CLK(\cd_sync.por_clk ),
.D(\cd_sync.$5[4] ),
.Q(\cd_sync.timer[4] )
);
/* module_not_derived = 1 */
/* src = "top.v:94.11-98.4|top.v:23.3-24.27|/usr/bin/../share/yosys/gowin/cells_map.v:19.7-19.56" */
DFFE \cd_sync.timer[5]_DFFE_Q (
.CE(\cd_sync.timer[5]_LUT4_I2_1_F ),
.CLK(\cd_sync.por_clk ),
.D(\cd_sync.$5[5] ),
.Q(\cd_sync.timer[5] )
);
/* module_not_derived = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:148.23-149.48" */
LUT4 \cd_sync.timer[5]_LUT4_I2 (
.F(\cd_sync.ready_DFFE_Q_CE ),
.I0(\cd_sync.timer[2]_LUT3_I0_F [0]),
.I1(\cd_sync.timer[2]_LUT3_I0_F [1]),
.I2(\cd_sync.timer[5] ),
.I3(\cd_sync.timer[3] )
);
defparam \cd_sync.timer[5]_LUT4_I2 .INIT = 16'h8000;
/* module_not_derived = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:148.23-149.48" */
LUT4 \cd_sync.timer[5]_LUT4_I2_1 (
.F(\cd_sync.timer[5]_LUT4_I2_1_F ),
.I0(\cd_sync.timer[2]_LUT3_I0_F [0]),
.I1(\cd_sync.timer[2]_LUT3_I0_F [1]),
.I2(\cd_sync.timer[5] ),
.I3(\cd_sync.timer[3] )
);
defparam \cd_sync.timer[5]_LUT4_I2_1 .INIT = 16'h7fff;
/* module_not_derived = 1 */
/* src = "top.v:94.11-98.4|top.v:23.3-24.27|/usr/bin/../share/yosys/gowin/cells_map.v:19.7-19.56" */
DFFE \cd_sync.timer[6]_DFFE_Q (
.CE(\cd_sync.timer[5]_LUT4_I2_1_F ),
.CLK(\cd_sync.por_clk ),
.D(\cd_sync.$5[6] ),
.Q(\cd_sync.timer[6] )
);
/* module_not_derived = 1 */
/* src = "top.v:94.11-98.4|top.v:23.3-24.27|/usr/bin/../share/yosys/gowin/cells_map.v:19.7-19.56" */
DFFE \cd_sync.timer[7]_DFFE_Q (
.CE(\cd_sync.timer[5]_LUT4_I2_1_F ),
.CLK(\cd_sync.por_clk ),
.D(\cd_sync.$5[7] ),
.Q(\cd_sync.timer[7] )
);
/* module_not_derived = 1 */
/* src = "top.v:94.11-98.4|top.v:23.3-24.27|/usr/bin/../share/yosys/gowin/cells_map.v:19.7-19.56" */
DFFE \cd_sync.timer[8]_DFFE_Q (
.CE(\cd_sync.timer[5]_LUT4_I2_1_F ),
.CLK(\cd_sync.por_clk ),
.D(\cd_sync.$5[8] ),
.Q(\cd_sync.timer[8] )
);
/* module_not_derived = 1 */
/* src = "top.v:92.3-93.39|/usr/bin/../share/yosys/gowin/cells_map.v:55.7-55.57" */
DFFS \led_counter[0]_DFFS_Q (
.CLK(\cd_sync.por_clk ),
.D(\$3[0] ),
.Q(\led_counter[0] ),
.SET(\cd_sync.ready_MUX2_LUT7_S0_O )
);
/* module_not_derived = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:148.23-149.48" */
LUT4 \led_counter[0]_LUT4_I0 (
.F(\led_counter[4]_LUT4_I0_F [0]),
.I0(\led_counter[0] ),
.I1(\led_counter[1] ),
.I2(\led_counter[2] ),
.I3(\led_counter[3] )
);
defparam \led_counter[0]_LUT4_I0 .INIT = 16'h0001;
/* module_not_derived = 1 */
/* src = "top.v:92.3-93.39|/usr/bin/../share/yosys/gowin/cells_map.v:31.7-31.59" */
DFFR \led_counter[10]_DFFR_Q (
.CLK(\cd_sync.por_clk ),
.D(\$3[10] ),
.Q(\led_counter[10] ),
.RESET(\cd_sync.ready_MUX2_LUT7_S0_O )
);
/* module_not_derived = 1 */
/* src = "top.v:92.3-93.39|/usr/bin/../share/yosys/gowin/cells_map.v:55.7-55.57" */
DFFS \led_counter[11]_DFFS_Q (
.CLK(\cd_sync.por_clk ),
.D(\$3[11] ),
.Q(\led_counter[11] ),
.SET(\cd_sync.ready_MUX2_LUT7_S0_O )
);
/* module_not_derived = 1 */
/* src = "top.v:92.3-93.39|/usr/bin/../share/yosys/gowin/cells_map.v:55.7-55.57" */
DFFS \led_counter[12]_DFFS_Q (
.CLK(\cd_sync.por_clk ),
.D(\$3[12] ),
.Q(\led_counter[12] ),
.SET(\cd_sync.ready_MUX2_LUT7_S0_O )
);
/* module_not_derived = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:148.23-149.48" */
LUT4 \led_counter[12]_LUT4_I0 (
.F(\led_counter[4]_LUT4_I0_F [1]),
.I0(\led_counter[12] ),
.I1(\led_counter[13] ),
.I2(\led_counter[14] ),
.I3(\led_counter[15] )
);
defparam \led_counter[12]_LUT4_I0 .INIT = 16'h0001;
/* module_not_derived = 1 */
/* src = "top.v:92.3-93.39|/usr/bin/../share/yosys/gowin/cells_map.v:31.7-31.59" */
DFFR \led_counter[13]_DFFR_Q (
.CLK(\cd_sync.por_clk ),
.D(\$3[13] ),
.Q(\led_counter[13] ),
.RESET(\cd_sync.ready_MUX2_LUT7_S0_O )
);
/* module_not_derived = 1 */
/* src = "top.v:92.3-93.39|/usr/bin/../share/yosys/gowin/cells_map.v:31.7-31.59" */
DFFR \led_counter[14]_DFFR_Q (
.CLK(\cd_sync.por_clk ),
.D(\$3[14] ),
.Q(\led_counter[14] ),
.RESET(\cd_sync.ready_MUX2_LUT7_S0_O )
);
/* module_not_derived = 1 */
/* src = "top.v:92.3-93.39|/usr/bin/../share/yosys/gowin/cells_map.v:31.7-31.59" */
DFFR \led_counter[15]_DFFR_Q (
.CLK(\cd_sync.por_clk ),
.D(\$3[15] ),
.Q(\led_counter[15] ),
.RESET(\cd_sync.ready_MUX2_LUT7_S0_O )
);
/* module_not_derived = 1 */
/* src = "top.v:92.3-93.39|/usr/bin/../share/yosys/gowin/cells_map.v:55.7-55.57" */
DFFS \led_counter[16]_DFFS_Q (
.CLK(\cd_sync.por_clk ),
.D(\$3[16] ),
.Q(\led_counter[16] ),
.SET(\cd_sync.ready_MUX2_LUT7_S0_O )
);
/* module_not_derived = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:148.23-149.48" */
LUT4 \led_counter[16]_LUT4_I0 (
.F(\led_counter[4]_LUT4_I0_F [4]),
.I0(\led_counter[16] ),
.I1(\led_counter[17] ),
.I2(\led_counter[18] ),
.I3(\led_counter[19] )
);
defparam \led_counter[16]_LUT4_I0 .INIT = 16'h0001;
/* module_not_derived = 1 */
/* src = "top.v:92.3-93.39|/usr/bin/../share/yosys/gowin/cells_map.v:55.7-55.57" */
DFFS \led_counter[17]_DFFS_Q (
.CLK(\cd_sync.por_clk ),
.D(\$3[17] ),
.Q(\led_counter[17] ),
.SET(\cd_sync.ready_MUX2_LUT7_S0_O )
);
/* module_not_derived = 1 */
/* src = "top.v:92.3-93.39|/usr/bin/../share/yosys/gowin/cells_map.v:55.7-55.57" */
DFFS \led_counter[18]_DFFS_Q (
.CLK(\cd_sync.por_clk ),
.D(\$3[18] ),
.Q(\led_counter[18] ),
.SET(\cd_sync.ready_MUX2_LUT7_S0_O )
);
/* module_not_derived = 1 */
/* src = "top.v:92.3-93.39|/usr/bin/../share/yosys/gowin/cells_map.v:31.7-31.59" */
DFFR \led_counter[19]_DFFR_Q (
.CLK(\cd_sync.por_clk ),
.D(\$3[19] ),
.Q(\led_counter[19] ),
.RESET(\cd_sync.ready_MUX2_LUT7_S0_O )
);
/* module_not_derived = 1 */
/* src = "top.v:92.3-93.39|/usr/bin/../share/yosys/gowin/cells_map.v:55.7-55.57" */
DFFS \led_counter[1]_DFFS_Q (
.CLK(\cd_sync.por_clk ),
.D(\$3[1] ),
.Q(\led_counter[1] ),
.SET(\cd_sync.ready_MUX2_LUT7_S0_O )
);
/* module_not_derived = 1 */
/* src = "top.v:92.3-93.39|/usr/bin/../share/yosys/gowin/cells_map.v:55.7-55.57" */
DFFS \led_counter[20]_DFFS_Q (
.CLK(\cd_sync.por_clk ),
.D(\$3[20] ),
.Q(\led_counter[20] ),
.SET(\cd_sync.ready_MUX2_LUT7_S0_O )
);
/* module_not_derived = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:148.23-149.48" */
LUT4 \led_counter[20]_LUT4_I0 (
.F(\led_counter[4]_LUT4_I0_F [3]),
.I0(\led_counter[20] ),
.I1(\led_counter[21] ),
.I2(\led_counter[22] ),
.I3(\led_counter[23] )
);
defparam \led_counter[20]_LUT4_I0 .INIT = 16'h0001;
/* module_not_derived = 1 */
/* src = "top.v:92.3-93.39|/usr/bin/../share/yosys/gowin/cells_map.v:55.7-55.57" */
DFFS \led_counter[21]_DFFS_Q (
.CLK(\cd_sync.por_clk ),
.D(\$3[21] ),
.Q(\led_counter[21] ),
.SET(\cd_sync.ready_MUX2_LUT7_S0_O )
);
/* module_not_derived = 1 */
/* src = "top.v:92.3-93.39|/usr/bin/../share/yosys/gowin/cells_map.v:31.7-31.59" */
DFFR \led_counter[22]_DFFR_Q (
.CLK(\cd_sync.por_clk ),
.D(\$3[22] ),
.Q(\led_counter[22] ),
.RESET(\cd_sync.ready_MUX2_LUT7_S0_O )
);
/* module_not_derived = 1 */
/* src = "top.v:92.3-93.39|/usr/bin/../share/yosys/gowin/cells_map.v:55.7-55.57" */
DFFS \led_counter[23]_DFFS_Q (
.CLK(\cd_sync.por_clk ),
.D(\$3[23] ),
.Q(\led_counter[23] ),
.SET(\cd_sync.ready_MUX2_LUT7_S0_O )
);
/* module_not_derived = 1 */
/* src = "top.v:92.3-93.39|/usr/bin/../share/yosys/gowin/cells_map.v:55.7-55.57" */
DFFS \led_counter[2]_DFFS_Q (
.CLK(\cd_sync.por_clk ),
.D(\$3[2] ),
.Q(\led_counter[2] ),
.SET(\cd_sync.ready_MUX2_LUT7_S0_O )
);
/* module_not_derived = 1 */
/* src = "top.v:92.3-93.39|/usr/bin/../share/yosys/gowin/cells_map.v:55.7-55.57" */
DFFS \led_counter[3]_DFFS_Q (
.CLK(\cd_sync.por_clk ),
.D(\$3[3] ),
.Q(\led_counter[3] ),
.SET(\cd_sync.ready_MUX2_LUT7_S0_O )
);
/* module_not_derived = 1 */
/* src = "top.v:92.3-93.39|/usr/bin/../share/yosys/gowin/cells_map.v:55.7-55.57" */
DFFS \led_counter[4]_DFFS_Q (
.CLK(\cd_sync.por_clk ),
.D(\$3[4] ),
.Q(\led_counter[4] ),
.SET(\cd_sync.ready_MUX2_LUT7_S0_O )
);
/* module_not_derived = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:148.23-149.48" */
LUT4 \led_counter[4]_LUT4_I0 (
.F(\led_counter[4]_LUT4_I0_F [5]),
.I0(\led_counter[4] ),
.I1(\led_counter[5] ),
.I2(\led_counter[6] ),
.I3(\led_counter[7] )
);
defparam \led_counter[4]_LUT4_I0 .INIT = 16'h0001;
/* module_not_derived = 1 */
/* src = "top.v:92.3-93.39|/usr/bin/../share/yosys/gowin/cells_map.v:55.7-55.57" */
DFFS \led_counter[5]_DFFS_Q (
.CLK(\cd_sync.por_clk ),
.D(\$3[5] ),
.Q(\led_counter[5] ),
.SET(\cd_sync.ready_MUX2_LUT7_S0_O )
);
/* module_not_derived = 1 */
/* src = "top.v:92.3-93.39|/usr/bin/../share/yosys/gowin/cells_map.v:55.7-55.57" */
DFFS \led_counter[6]_DFFS_Q (
.CLK(\cd_sync.por_clk ),
.D(\$3[6] ),
.Q(\led_counter[6] ),
.SET(\cd_sync.ready_MUX2_LUT7_S0_O )
);
/* module_not_derived = 1 */
/* src = "top.v:92.3-93.39|/usr/bin/../share/yosys/gowin/cells_map.v:55.7-55.57" */
DFFS \led_counter[7]_DFFS_Q (
.CLK(\cd_sync.por_clk ),
.D(\$3[7] ),
.Q(\led_counter[7] ),
.SET(\cd_sync.ready_MUX2_LUT7_S0_O )
);
/* module_not_derived = 1 */
/* src = "top.v:92.3-93.39|/usr/bin/../share/yosys/gowin/cells_map.v:31.7-31.59" */
DFFR \led_counter[8]_DFFR_Q (
.CLK(\cd_sync.por_clk ),
.D(\$3[8] ),
.Q(\led_counter[8] ),
.RESET(\cd_sync.ready_MUX2_LUT7_S0_O )
);
/* module_not_derived = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:148.23-149.48" */
LUT4 \led_counter[8]_LUT4_I0 (
.F(\led_counter[4]_LUT4_I0_F [2]),
.I0(\led_counter[8] ),
.I1(\led_counter[9] ),
.I2(\led_counter[10] ),
.I3(\led_counter[11] )
);
defparam \led_counter[8]_LUT4_I0 .INIT = 16'h0001;
/* module_not_derived = 1 */
/* src = "top.v:92.3-93.39|/usr/bin/../share/yosys/gowin/cells_map.v:55.7-55.57" */
DFFS \led_counter[9]_DFFS_Q (
.CLK(\cd_sync.por_clk ),
.D(\$3[9] ),
.Q(\led_counter[9] ),
.SET(\cd_sync.ready_MUX2_LUT7_S0_O )
);
/* hdlname = "pin_clk24_0 clk24_0_0" */
/* module_not_derived = 1 */
/* src = "top.v:99.15-102.4|top.v:55.8-58.4" */
IBUF \pin_clk24_0.clk24_0_0 (
.I(clk24_0__io),
.O(\cd_sync.por_clk )
);
/* hdlname = "pin_led_0 led_0_0" */
/* module_not_derived = 1 */
/* src = "top.v:103.13-106.4|top.v:64.8-67.4" */
OBUF \pin_led_0.led_0_0 (
.I(pin_led_0_led_0__o),
.O(\pin_led_0.led_0__io )
);
/* module_not_derived = 1 */
/* src = "top.v:90.3-91.53|/usr/bin/../share/yosys/gowin/cells_map.v:43.8-43.68" */
DFFRE pin_led_0_led_0__o_DFFRE_Q (
.CE(pin_led_0_led_0__o_DFFRE_Q_CE),
.CLK(\cd_sync.por_clk ),
.D(\$8 ),
.Q(pin_led_0_led_0__o),
.RESET(pin_led_0_led_0__o_DFFRE_Q_RESET)
);
/* module_not_derived = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:161.14-161.54" */
MUX2_LUT6 pin_led_0_led_0__o_DFFRE_Q_CE_MUX2_LUT6_O (
.I0(pin_led_0_led_0__o_DFFRE_Q_CE_MUX2_LUT6_O_I0),
.I1(pin_led_0_led_0__o_DFFRE_Q_CE_MUX2_LUT6_O_I1),
.O(pin_led_0_led_0__o_DFFRE_Q_CE),
.S0(\led_counter[4]_LUT4_I0_F [4]));
/* module_not_derived = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:159.41-159.66|/usr/bin/../share/yosys/gowin/cells_map.v:155.14-155.54" */
MUX2_LUT5 pin_led_0_led_0__o_DFFRE_Q_CE_MUX2_LUT6_O_I0_MUX2_LUT5_O (
.I0(\cd_sync.initial ),
.I1(\cd_sync.initial ),
.O(pin_led_0_led_0__o_DFFRE_Q_CE_MUX2_LUT6_O_I0),
.S0(\led_counter[4]_LUT4_I0_F [3])
);
/* module_not_derived = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:160.41-160.66|/usr/bin/../share/yosys/gowin/cells_map.v:155.14-155.54" */
MUX2_LUT5 pin_led_0_led_0__o_DFFRE_Q_CE_MUX2_LUT6_O_I1_MUX2_LUT5_O (
.I0(\cd_sync.initial ),
.I1(pin_led_0_led_0__o_DFFRE_Q_CE_MUX2_LUT6_O_I1_MUX2_LUT5_O_I1),
.O(pin_led_0_led_0__o_DFFRE_Q_CE_MUX2_LUT6_O_I1),
.S0(\led_counter[4]_LUT4_I0_F [3])
);
/* module_not_derived = 1 */
/* src = "/usr/bin/../share/yosys/gowin/cells_map.v:160.41-160.66|/usr/bin/../share/yosys/gowin/cells_map.v:154.41-154.66|/usr/bin/../share/yosys/gowin/cells_map.v:148.23-149.48" */
LUT4 pin_led_0_led_0__o_DFFRE_Q_CE_MUX2_LUT6_O_I1_MUX2_LUT5_O_I1_LUT4_F (
.F(pin_led_0_led_0__o_DFFRE_Q_CE_MUX2_LUT6_O_I1_MUX2_LUT5_O_I1),
.I0(\led_counter[4]_LUT4_I0_F [5]),
.I1(\led_counter[4]_LUT4_I0_F [0]),
.I2(\led_counter[4]_LUT4_I0_F [1]),
.I3(\led_counter[4]_LUT4_I0_F [2])
);
defparam pin_led_0_led_0__o_DFFRE_Q_CE_MUX2_LUT6_O_I1_MUX2_LUT5_O_I1_LUT4_F.INIT = 16'h8000;
assign \led_counter[4]_LUT4_I0_F [6] = \cd_sync.ready ;
assign \cd_sync.timer[2]_LUT3_I0_F [3:2] = { \cd_sync.timer[3] , \cd_sync.timer[5] };
assign \$4[0] = \$3[0] ;
assign \$4[10] = \$3[10] ;
assign \$4[11] = \$3[11] ;
assign \$4[12] = \$3[12] ;
assign \$4[13] = \$3[13] ;
assign \$4[14] = \$3[14] ;
assign \$4[15] = \$3[15] ;
assign \$4[16] = \$3[16] ;
assign \$4[17] = \$3[17] ;
assign \$4[18] = \$3[18] ;
assign \$4[19] = \$3[19] ;
assign \$4[1] = \$3[1] ;
assign \$4[20] = \$3[20] ;
assign \$4[21] = \$3[21] ;
assign \$4[22] = \$3[22] ;
assign \$4[23] = \$3[23] ;
assign \$4[24] = \cd_sync.initial ;
assign \$4[2] = \$3[2] ;
assign \$4[3] = \$3[3] ;
assign \$4[4] = \$3[4] ;
assign \$4[5] = \$3[5] ;
assign \$4[6] = \$3[6] ;
assign \$4[7] = \$3[7] ;
assign \$4[8] = \$3[8] ;
assign \$4[9] = \$3[9] ;
assign \cd_sync.clk = \cd_sync.por_clk ;
assign \cd_sync.clk24_0__i = \cd_sync.por_clk ;
assign cd_sync_clk24_0__i = \cd_sync.por_clk ;
assign clk = \cd_sync.por_clk ;
assign \initial = \cd_sync.initial ;
assign led_0__io = \pin_led_0.led_0__io ;
assign \pin_clk24_0.clk24_0__i = \cd_sync.por_clk ;
assign \pin_clk24_0.clk24_0__io = clk24_0__io;
assign \pin_led_0.led_0__o = pin_led_0_led_0__o;
endmodule
Raw
top.ys
#read_ilang top.il
# Read verilog instead, makes the output slightly different but the bug persists
read_verilog top.debug.v
synth_gowin -top top -vout top.vg
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