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jiangaojie
brabect1
/ sta_cdc_paths.rst
Last active
September 19, 2024 22:07
Timing constraints for clock-domain crossings. #sta #cdc
rajesh-s
/ axi_discussion.md
Created
March 1, 2020 08:04
A summary of AXI discussion on the thread https://www.reddit.com/r/FPGA/comments/egkrce/is_axi_too_complicated/
**Note: In all below, slave can also mean interconnect
- Do we really need back-pressure?
- Yes, you absolutely need backpressure. What happens when two masters want to access the same slave? One has to be blocked for some period of time. Some slaves may only be able to handle a limited number of concurrent operations and take some time to produce a result. As such, backpressure is required.
- B and R channel backpressure is required in the case of contention towards the master. If a master makes burst read requests against two different slaves, one of them is gonna have to wait.
- Shouldn't a master be prepared to receive the responses for any requests it issues from the moment it makes the request? Aside from the clock crossing issue someone else brought up, and the interconnect issue at the heart of the use of IDs, why should an AXI master ever stall R or B channels?
- The master should be prepared, but it only has one R and one B input, so it can't re