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@jck
Created March 12, 2014 21:15
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from myhdl import *
def ab(in1,out1):
one=[Signal(intbv(0)[2:]) for k in range(2)]
@always_comb
def comb1():
one[0].next[0]=in1 #conv_run requires: one[0][0].next=in1
@always_comb
def comb2():
out1.next=one[0][0]
return instances()
def sim_dut():
in1,out1=[Signal(intbv(0)[2:]) for k in range(2)]
dut=ab(in1,out1)
@instance
def stimulus():
for k in range(2):
in1.next=k
yield delay(5)
print out1
raise StopSimulation
return instances()
def sim_run():
tb_inst=sim_dut()
sim=Simulation(tb_inst)
sim.run()
def conv_run():
in1,out1=[Signal(intbv(0)[2:]) for k in range(2)]
dd=toVerilog(ab,in1,out1)
conv_run()
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