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----------------------------------------------------------------------------------- |
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--! @file reducer_test_model.vhd |
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--! @brief TEST MODEL for REDUCER : |
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--! @version 1.0.0 |
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--! @date 2012/4/3 |
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--! @author Ichiro Kawazome <ichiro_k@ca2.so-net.ne.jp> |
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----------------------------------------------------------------------------------- |
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-- |
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-- Copyright (C) 2012 Ichiro Kawazome |
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-- All rights reserved. |
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-- |
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-- Redistribution and use in source and binary forms, with or without |
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-- modification, are permitted provided that the following conditions |
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-- are met: |
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-- |
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-- 1. Redistributions of source code must retain the above copyright |
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-- notice, this list of conditions and the following disclaimer. |
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-- |
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-- 2. Redistributions in binary form must reproduce the above copyright |
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-- notice, this list of conditions and the following disclaimer in |
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-- the documentation and/or other materials provided with the |
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-- distribution. |
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-- |
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
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-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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-- OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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-- |
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----------------------------------------------------------------------------------- |
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library ieee; |
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use ieee.std_logic_1164.all; |
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package RANDOM_DATA_TABLE is |
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procedure GET( |
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WIDTH : in integer; |
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OFFSET : in integer; |
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ADDR : in integer; |
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SIZE : in integer; |
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LEN : out integer; |
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DATA : out std_logic_vector; |
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ENBL : out std_logic_vector; |
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DONE : out std_logic); |
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constant TABLE_SIZE : integer := 4096; |
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constant ERROR_CODE : std_logic_vector(7 downto 0) := "11001100"; |
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end RANDOM_DATA_TABLE; |
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----------------------------------------------------------------------------------- |
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-- |
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----------------------------------------------------------------------------------- |
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library ieee; |
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use ieee.std_logic_1164.all; |
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use ieee.numeric_std.all; |
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use ieee.math_real.uniform; |
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use std.textio.all; |
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package body RANDOM_DATA_TABLE is |
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|
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type DATA_TABLE_TYPE is array (INTEGER range <>) of std_logic_vector(7 downto 0); |
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|
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function DATA_TABLE_GEN(SIZE:integer) return DATA_TABLE_TYPE is |
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variable table : DATA_TABLE_TYPE(0 to SIZE-1); |
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variable seed1 : integer := 1234; |
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variable seed2 : integer := 5678; |
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variable rnd_num : real; |
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variable pattern : integer range 0 to 255; |
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begin |
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for i in table'range loop |
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UNIFORM(seed1,seed2,rnd_num); |
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pattern := integer(rnd_num*255.0); |
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while (pattern = TO_INTEGER(unsigned(ERROR_CODE))) loop |
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UNIFORM(seed1,seed2,rnd_num); |
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pattern := integer(rnd_num*255.0); |
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end loop; |
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table(i) := std_logic_vector(TO_UNSIGNED(pattern,8)); |
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end loop; |
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return table; |
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end function; |
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|
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constant DATA_TABLE : DATA_TABLE_TYPE(0 to TABLE_SIZE-1) := DATA_TABLE_GEN(TABLE_SIZE); |
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|
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procedure GET( WIDTH : in integer; |
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OFFSET : in integer; |
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ADDR : in integer; |
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SIZE : in integer; |
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LEN : out integer; |
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DATA : out std_logic_vector; |
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ENBL : out std_logic_vector; |
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DONE : out std_logic) is |
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variable o_data : std_logic_vector(8*WIDTH-1 downto 0); |
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variable o_enbl : std_logic_vector( WIDTH-1 downto 0); |
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variable f_enbl : std_logic_vector( WIDTH-1 downto 0); |
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variable l_enbl : std_logic_vector( WIDTH-1 downto 0); |
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variable length : integer; |
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variable addr_end : integer range 0 to TABLE_SIZE-1; |
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begin |
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addr_end := OFFSET + SIZE - 1; |
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for i in f_enbl'range loop |
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if (i >= OFFSET) then |
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f_enbl(i) := '1'; |
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else |
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f_enbl(i) := '0'; |
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end if; |
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end loop; |
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for i in l_enbl'range loop |
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if (i <= addr_end) then |
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l_enbl(i) := '1'; |
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else |
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l_enbl(i) := '0'; |
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end if; |
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end loop; |
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if (addr_end < WIDTH) then |
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DONE := '1'; |
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else |
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DONE := '0'; |
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end if; |
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o_enbl := f_enbl and l_enbl; |
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length := 0; |
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for i in o_enbl'range loop |
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if (o_enbl(i) = '1') then |
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length := length + 1; |
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o_data((i+1)*8-1 downto i*8) := DATA_TABLE(ADDR-OFFSET+i); |
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else |
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o_data((i+1)*8-1 downto i*8) := ERROR_CODE; |
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end if; |
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end loop; |
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DATA := o_data; |
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ENBL := o_enbl; |
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LEN := length; |
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end GET; |
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end RANDOM_DATA_TABLE; |
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----------------------------------------------------------------------------------- |
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-- |
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----------------------------------------------------------------------------------- |
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library ieee; |
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use ieee.std_logic_1164.all; |
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entity REDUCER_TEST_MODEL is |
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generic ( |
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NAME : string; |
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DELAY : time; |
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WORD_BITS : integer := 32; |
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I_WIDTH : integer := 1; |
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O_WIDTH : integer := 4; |
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I_JUSTIFIED : integer := 0; |
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FLUSH_ENABLE : integer := 0; |
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AUTO_FINISH : integer := 1 |
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); |
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port( |
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CLK : in std_logic; |
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RST : out std_logic; |
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CLR : out std_logic; |
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START : out std_logic; |
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OFFSET : out std_logic_vector(O_WIDTH-1 downto 0); |
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DONE : out std_logic; |
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FLUSH : out std_logic; |
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I_DATA : out std_logic_vector(I_WIDTH*(WORD_BITS )-1 downto 0); |
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I_ENBL : out std_logic_vector(I_WIDTH*(WORD_BITS/8)-1 downto 0); |
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I_FLUSH : out std_logic; |
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I_DONE : out std_logic; |
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I_VAL : out std_logic; |
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I_RDY : in std_logic := '0'; |
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O_DATA : in std_logic_vector(O_WIDTH*(WORD_BITS )-1 downto 0) := (others => '0'); |
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O_ENBL : in std_logic_vector(O_WIDTH*(WORD_BITS/8)-1 downto 0) := (others => '1'); |
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O_FLUSH : in std_logic := '0'; |
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O_DONE : in std_logic := '0'; |
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O_VAL : in std_logic := '0'; |
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O_RDY : out std_logic; |
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BUSY : in std_logic; |
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FINISH : out std_logic |
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); |
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end REDUCER_TEST_MODEL; |
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----------------------------------------------------------------------------------- |
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-- |
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----------------------------------------------------------------------------------- |
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library ieee; |
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use ieee.std_logic_1164.all; |
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use ieee.numeric_std.all; |
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use std.textio.all; |
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use WORK.RANDOM_DATA_TABLE; |
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architecture MODEL of REDUCER_TEST_MODEL is |
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constant I_BYTES : integer := I_WIDTH*WORD_BITS/8; |
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constant O_BYTES : integer := O_WIDTH*WORD_BITS/8; |
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constant HEX : STRING(1 to 16) := "0123456789ABCDEF"; |
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signal SCENARIO : STRING(1 to 5); |
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signal RECV_REQ : boolean; |
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signal RECV_ACK : boolean; |
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signal RECV_FLUSH : boolean; |
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signal RECV_EOD : boolean; |
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signal RECV_ADDR : integer; |
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signal RECV_SIZE : integer; |
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signal RECV_MODE : integer; |
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signal i_valid : std_logic; |
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signal o_ready : std_logic; |
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------------------------------------------------------------------------------- |
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-- |
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------------------------------------------------------------------------------- |
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-- function INT_TO_STRING(arg:integer;len:integer;space:character) return STRING is |
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-- variable str : STRING(1 to len); |
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-- variable value : integer; |
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-- begin |
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-- value := arg; |
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-- for i in str'right downto str'left loop |
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-- if (value > 0) then |
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-- case (value mod 10) is |
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-- when 0 => str(i) := '0'; |
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-- when 1 => str(i) := '1'; |
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-- when 2 => str(i) := '2'; |
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-- when 3 => str(i) := '3'; |
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-- when 4 => str(i) := '4'; |
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-- when 5 => str(i) := '5'; |
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-- when 6 => str(i) := '6'; |
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-- when 7 => str(i) := '7'; |
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-- when 8 => str(i) := '8'; |
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-- when 9 => str(i) := '9'; |
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-- when others => str(i) := 'X'; |
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-- end case; |
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-- else |
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-- if (i = str'right) then |
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-- str(i) := '0'; |
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-- else |
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-- str(i) := space; |
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-- end if; |
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-- end if; |
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-- value := value / 10; |
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-- end loop; |
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-- return str; |
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-- end INT_TO_STRING; |
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begin |
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------------------------------------------------------------------------------- |
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-- |
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------------------------------------------------------------------------------- |
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process |
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--------------------------------------------------------------------------- |
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-- |
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--------------------------------------------------------------------------- |
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procedure WAIT_CLK(CNT:integer) is |
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begin |
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if (CNT > 0) then |
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for i in 1 to CNT loop |
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wait until (CLK'event and CLK = '1'); |
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end loop; |
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end if; |
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wait for DELAY; |
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end WAIT_CLK; |
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--------------------------------------------------------------------------- |
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-- |
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--------------------------------------------------------------------------- |
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procedure RECV_START (ADDR,SIZE,MODE:integer;FLUSH,EOD:boolean) is |
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begin |
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RECV_REQ <= TRUE; |
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RECV_ADDR <= ADDR; |
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RECV_SIZE <= SIZE; |
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RECV_MODE <= MODE; |
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RECV_FLUSH<= FLUSH; |
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RECV_EOD <= EOD; |
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wait until (CLK'event and CLK = '1' and RECV_ACK = TRUE); |
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wait for DELAY; |
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RECV_REQ <= FALSE; |
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end RECV_START; |
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--------------------------------------------------------------------------- |
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-- |
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--------------------------------------------------------------------------- |
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procedure RECV_END is |
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begin |
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wait until (CLK'event and CLK = '1' and RECV_ACK = FALSE); |
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wait for DELAY; |
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end RECV_END; |
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--------------------------------------------------------------------------- |
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-- |
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--------------------------------------------------------------------------- |
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procedure OUTPUT(ADDR,SIZE:integer;INITIALIZE,LAST,FLUSH:boolean) is |
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variable data : std_logic_vector(I_DATA'range); |
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variable enbl : std_logic_vector(I_ENBL'range); |
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variable valid : std_logic; |
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variable end_of_data : std_logic; |
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variable pos : integer; |
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variable bytes : integer; |
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variable len : integer; |
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variable lo_pos : integer; |
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variable num : integer; |
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begin |
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if (INITIALIZE and O_WIDTH > 1) then |
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for i in OFFSET'range loop |
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if (i < ((ADDR rem O_BYTES)/(WORD_BITS/8))) then |
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OFFSET(i) <= '1'; |
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else |
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OFFSET(i) <= '0'; |
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end if; |
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end loop; |
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START <= '1'; |
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end if; |
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pos := ADDR; |
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bytes := SIZE; |
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while (bytes > 0) loop |
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lo_pos := pos rem I_BYTES; |
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RANDOM_DATA_TABLE.GET(I_BYTES,lo_pos,pos,bytes,len,data,enbl,end_of_data); |
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pos := pos + len; |
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bytes := bytes - len; |
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if (I_JUSTIFIED > 0 and enbl(0) = '0') then |
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num := 1; |
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for i in 1 to enbl'high loop |
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if (enbl(i) = '1') then |
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num := i; |
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exit; |
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end if; |
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end loop; |
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for i in enbl'low to enbl'high loop |
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if (i+num > enbl'high) then |
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I_DATA(8*(i+1)-1 downto 8*i) <= (others => '0'); |
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I_ENBL( i) <= '0'; |
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else |
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I_DATA(8*(i+1)-1 downto 8*i) <= data(8*(i+1+num)-1 downto 8*(i+num)); |
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I_ENBL( i) <= enbl(i+num); |
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end if; |
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end loop; |
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else |
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I_DATA <= data; |
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I_ENBL <= enbl; |
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end if; |
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if (LAST) then |
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I_DONE <= end_of_data; |
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else |
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I_DONE <= '0'; |
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end if; |
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if (FLUSH) then |
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I_FLUSH <= end_of_data; |
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else |
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I_FLUSH <= '0'; |
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end if; |
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I_VAL <= '1'; |
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i_valid <= '1'; |
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wait until (CLK'event and CLK = '1' and I_RDY = '1'); |
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wait for DELAY; |
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START <= '0'; |
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I_VAL <= '0'; |
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i_valid <= '0'; |
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I_DONE <= '0'; |
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I_FLUSH <= '0'; |
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I_DATA <= (others => '1'); |
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I_ENBL <= (others => '1'); |
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end loop; |
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end procedure; |
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--------------------------------------------------------------------------- |
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-- |
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--------------------------------------------------------------------------- |
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procedure OUTPUT(ADDR,SIZE:integer) is |
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begin |
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OUTPUT(ADDR,SIZE,TRUE,TRUE,FALSE); |
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end procedure; |
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--------------------------------------------------------------------------- |
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-- |
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--------------------------------------------------------------------------- |
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variable max_addr : integer; |
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variable max_size : integer; |
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variable addr : integer; |
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variable remain_size : integer; |
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variable block_size : integer; |
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variable initialize : boolean; |
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--------------------------------------------------------------------------- |
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-- |
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--------------------------------------------------------------------------- |
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procedure DONE_REQ is |
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begin |
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DONE <= '1'; |
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wait until (CLK'event and CLK = '1'); |
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wait for DELAY; |
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DONE <= '0'; |
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end procedure; |
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--------------------------------------------------------------------------- |
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-- |
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--------------------------------------------------------------------------- |
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procedure FLUSH_REQ is |
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begin |
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FLUSH <= '1'; |
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wait until (CLK'event and CLK = '1'); |
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wait for DELAY; |
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FLUSH <= '0'; |
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end procedure; |
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begin |
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--------------------------------------------------------------------------- |
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-- |
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--------------------------------------------------------------------------- |
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if (I_BYTES > O_BYTES) then |
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max_addr := I_BYTES; |
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max_size := (I_BYTES/O_BYTES)*(I_BYTES*5); |
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else |
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max_addr := O_BYTES; |
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max_size := (O_BYTES/I_BYTES)*(O_BYTES*5); |
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end if; |
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--------------------------------------------------------------------------- |
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-- シミュレーションの開始、まずはリセットから。 |
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--------------------------------------------------------------------------- |
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assert(false) report "Starting Run..." severity NOTE; |
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SCENARIO <= "START"; |
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RST <= '1'; |
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CLR <= '1'; |
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START <= '0'; |
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OFFSET <= (others => '0'); |
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DONE <= '0'; |
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FLUSH <= '0'; |
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I_DATA <= (others => '0'); |
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I_ENBL <= (others => '0'); |
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I_FLUSH <= '0'; |
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I_DONE <= '0'; |
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I_VAL <= '0'; |
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i_valid <= '0'; |
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WAIT_CLK( 4); RST <= '0'; |
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CLR <= '0'; |
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WAIT_CLK( 4); |
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--------------------------------------------------------------------------- |
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-- |
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--------------------------------------------------------------------------- |
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SCENARIO <= "1.0.0"; |
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for size in 1 to max_size loop |
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for pos in 0 to max_addr loop |
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addr := pos*max_addr+pos; |
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RECV_START(addr,size,0,FALSE,TRUE); |
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OUTPUT (addr,size ); |
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RECV_END; |
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end loop; |
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end loop; |
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--------------------------------------------------------------------------- |
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-- |
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--------------------------------------------------------------------------- |
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SCENARIO <= "2.0.0"; |
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for size in 1 to max_size loop |
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for pos in 0 to max_addr loop |
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addr := pos*max_addr+pos; |
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RECV_START(addr,size,1,FALSE,TRUE); |
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OUTPUT (addr,size ); |
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RECV_END; |
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end loop; |
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end loop; |
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--------------------------------------------------------------------------- |
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-- |
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--------------------------------------------------------------------------- |
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SCENARIO <= "3.0.0"; |
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for size in 1 to max_size loop |
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for pos in 0 to max_addr loop |
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addr := pos*max_addr+pos; |
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RECV_START(addr,size,2,FALSE,TRUE); |
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OUTPUT (addr,size ); |
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RECV_END; |
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end loop; |
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end loop; |
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--------------------------------------------------------------------------- |
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-- |
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--------------------------------------------------------------------------- |
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SCENARIO <= "4.0.0"; |
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if (WORD_BITS = 8 and I_WIDTH > 1) then |
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for size in 8 to 33 loop |
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for block_size in 1 to 11 loop |
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addr := 0; |
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remain_size := size; |
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RECV_START(addr,size,0,FALSE,TRUE); |
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initialize := TRUE; |
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while (remain_size > 0) loop |
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if (remain_size <= block_size) then |
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OUTPUT(addr,remain_size,initialize, TRUE ,FALSE); |
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addr := addr + remain_size; |
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remain_size := 0; |
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else |
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OUTPUT(addr,block_size ,initialize, FALSE,FALSE); |
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addr := addr + block_size; |
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remain_size := remain_size - block_size; |
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end if; |
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initialize := FALSE; |
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end loop; |
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RECV_END; |
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end loop; |
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end loop; |
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end if; |
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--------------------------------------------------------------------------- |
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-- |
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--------------------------------------------------------------------------- |
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SCENARIO <= "5.0.0"; |
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if (WORD_BITS = 8 and I_WIDTH > 1) then |
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for size in 8 to 15 loop |
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for block_size in 1 to 11 loop |
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for wait_count in 0 to 3 loop |
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addr := 0; |
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remain_size := size; |
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RECV_START(addr,size,0,FALSE,FALSE); |
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initialize := TRUE; |
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while (remain_size > 0) loop |
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if (remain_size <= block_size) then |
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OUTPUT(addr,remain_size,initialize, FALSE,FALSE); |
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addr := addr + remain_size; |
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remain_size := 0; |
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else |
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OUTPUT(addr,block_size ,initialize, FALSE,FALSE); |
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addr := addr + block_size; |
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remain_size := remain_size - block_size; |
|
end if; |
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initialize := FALSE; |
|
end loop; |
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WAIT_CLK(wait_count); |
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DONE_REQ; |
|
RECV_END; |
|
end loop; |
|
end loop; |
|
end loop; |
|
end if; |
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--------------------------------------------------------------------------- |
|
-- |
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--------------------------------------------------------------------------- |
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SCENARIO <= "6.0.0";wait for 0 ns; |
|
if (FLUSH_ENABLE > 0 and WORD_BITS = 8 and I_WIDTH > 1) then |
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for size in 8 to 33 loop |
|
for block_size in 1 to 11 loop |
|
addr := 0; |
|
remain_size := size; |
|
initialize := TRUE; |
|
while (remain_size > 0) loop |
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-- assert false report NAME & ":" & SCENARIO & |
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-- " addr=" & INT_TO_STRING(addr,4,'0') & |
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-- " size=" & INT_TO_STRING(size,4,'0') & |
|
-- " remain_size=" & INT_TO_STRING(remain_size,4,'0') & |
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-- " block_size=" & INT_TO_STRING(block_size ,4,'0') severity note; |
|
if (remain_size <= block_size) then |
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RECV_START(addr,remain_size,0,FALSE,TRUE); |
|
OUTPUT(addr,remain_size,initialize, TRUE ,FALSE); |
|
RECV_END; |
|
addr := addr + remain_size; |
|
remain_size := 0; |
|
else |
|
RECV_START(addr,block_size, 0,TRUE, TRUE); |
|
OUTPUT(addr,block_size ,initialize, FALSE,TRUE ); |
|
RECV_END; |
|
addr := addr + block_size; |
|
remain_size := remain_size - block_size; |
|
end if; |
|
initialize := FALSE; |
|
end loop; |
|
end loop; |
|
end loop; |
|
end if; |
|
--------------------------------------------------------------------------- |
|
-- シミュレーション終了 |
|
--------------------------------------------------------------------------- |
|
WAIT_CLK(10); |
|
SCENARIO <= "DONE."; |
|
WAIT_CLK(10); |
|
if (AUTO_FINISH = 0) then |
|
assert(false) report NAME & " Run complete..." severity NOTE; |
|
FINISH <= 'Z'; |
|
else |
|
FINISH <= 'Z'; |
|
assert(false) report NAME & " Run complete..." severity FAILURE; |
|
end if; |
|
wait; |
|
end process; |
|
------------------------------------------------------------------------------- |
|
-- |
|
------------------------------------------------------------------------------- |
|
RECV:process |
|
variable addr : integer; |
|
variable size : integer; |
|
variable len : integer; |
|
variable lo_pos : integer; |
|
variable data : std_logic_vector(O_DATA'range); |
|
variable enbl : std_logic_vector(O_ENBL'range); |
|
variable end_of_data : std_logic; |
|
variable data_ok : boolean; |
|
begin |
|
RECV_ACK <= FALSE; |
|
O_RDY <= '0'; |
|
o_ready <= '0'; |
|
RECV_LOOP: loop |
|
wait until (CLK'event and CLK = '1' and RECV_REQ = TRUE); |
|
wait for DELAY; |
|
RECV_ACK <= TRUE; |
|
if (RECV_MODE = 0) then |
|
O_RDY <= '1'; |
|
o_ready <= '1'; |
|
else |
|
O_RDY <= '0'; |
|
o_ready <= '0'; |
|
end if; |
|
addr := RECV_ADDR; |
|
size := RECV_SIZE; |
|
CHK_LOOP: loop |
|
wait until (CLK'event and CLK = '1' and O_VAL = '1'); |
|
if (RECV_MODE > 0) then |
|
if (RECV_MODE > 1) then |
|
for i in 2 to RECV_MODE loop |
|
wait until (CLK'event and CLK = '1'); |
|
end loop; |
|
end if; |
|
wait for DELAY; |
|
O_RDY <= '1'; |
|
o_ready <= '1'; |
|
wait until (CLK'event and CLK = '1' and O_VAL = '1'); |
|
end if; |
|
lo_pos := addr rem O_BYTES; |
|
RANDOM_DATA_TABLE.GET(O_BYTES,lo_pos,addr,size,len,data,enbl,end_of_data); |
|
addr := addr + len; |
|
size := size - len; |
|
assert (O_ENBL = enbl) report NAME & " Mismatch O_ENBL" severity FAILURE; |
|
data_ok := TRUE; |
|
for i in O_ENBL'range loop |
|
if (O_ENBL(i) = '1') then |
|
if (O_DATA((i+1)*8-1 downto i*8) /= data((i+1)*8-1 downto i*8)) then |
|
data_ok := FALSE; |
|
end if; |
|
end if; |
|
end loop; |
|
assert (data_ok) report NAME & " Mismatch O_DATA" severity FAILURE; |
|
if (RECV_EOD = TRUE) then |
|
if (FLUSH_ENABLE > 0 and RECV_FLUSH) then |
|
assert (O_FLUSH = end_of_data) |
|
report NAME & " Mismatch O_FLUSH" severity FAILURE; |
|
else |
|
assert (O_DONE = end_of_data) |
|
report NAME & " Mismatch O_DONE" severity FAILURE; |
|
end if; |
|
end if; |
|
exit CHK_LOOP when (end_of_data = '1'); |
|
wait for DELAY; |
|
if (RECV_MODE > 0) then |
|
O_RDY <= '0'; |
|
o_ready <= '0'; |
|
end if; |
|
end loop; |
|
if (RECV_EOD = FALSE) then |
|
if (FLUSH_ENABLE > 0 and RECV_FLUSH) then |
|
if (O_FLUSH = '0') then |
|
wait until (CLK'event and CLK = '1' and O_FLUSH = '1'); |
|
end if; |
|
else |
|
if (O_DONE = '0') then |
|
wait until (CLK'event and CLK = '1' and O_DONE = '1'); |
|
end if; |
|
end if; |
|
end if; |
|
wait for DELAY; |
|
RECV_ACK <= FALSE; |
|
O_RDY <= '0'; |
|
o_ready <= '0'; |
|
end loop; |
|
end process; |
|
------------------------------------------------------------------------------- |
|
-- |
|
------------------------------------------------------------------------------- |
|
CHECK_BUSY: process begin |
|
RECV_LOOP: loop |
|
wait until (CLK'event and CLK = '1' and RECV_ACK = TRUE); |
|
CHK_LOOP_0: loop |
|
wait until (CLK'event and CLK = '1'); |
|
assert (BUSY = '0') |
|
report NAME & " Mismatch BUSY /= '0'" severity FAILURE; |
|
exit CHK_LOOP_0 when (i_valid = '1' and I_RDY = '1'); |
|
end loop; |
|
CHK_LOOP_1: loop |
|
wait until (CLK'event and CLK = '1'); |
|
assert (BUSY = '1') |
|
report NAME & " Mismatch BUSY /= '1'" severity FAILURE; |
|
exit CHK_LOOP_1 when (O_VAL = '1' and o_ready = '1' and O_DONE = '1') or |
|
(O_VAL = '1' and o_ready = '1' and O_FLUSH = '1'); |
|
end loop; |
|
CHK_LOOP_2: loop |
|
wait until (CLK'event and CLK = '1'); |
|
assert (BUSY = '0') |
|
report NAME & " Mismatch BUSY /= '0'" severity FAILURE; |
|
exit CHK_LOOP_2 when (RECV_ACK = FALSE); |
|
end loop; |
|
end loop; |
|
end process; |
|
end MODEL; |
|
----------------------------------------------------------------------------------- |
|
-- |
|
----------------------------------------------------------------------------------- |
|
library ieee; |
|
use ieee.std_logic_1164.all; |
|
package COMPONENTS is |
|
component REDUCER is |
|
generic ( |
|
WORD_BITS : integer; |
|
ENBL_BITS : integer; |
|
I_WIDTH : integer; |
|
O_WIDTH : integer; |
|
QUEUE_SIZE : integer; |
|
VALID_MIN : integer; |
|
VALID_MAX : integer; |
|
I_JUSTIFIED : integer; |
|
FLUSH_ENABLE: integer |
|
); |
|
port ( |
|
CLK : in std_logic; |
|
RST : in std_logic; |
|
CLR : in std_logic; |
|
START : in std_logic; |
|
OFFSET : in std_logic_vector(O_WIDTH-1 downto 0); |
|
DONE : in std_logic; |
|
FLUSH : in std_logic; |
|
BUSY : out std_logic; |
|
VALID : out std_logic_vector(VALID_MAX downto VALID_MIN); |
|
I_DATA : in std_logic_vector(I_WIDTH*WORD_BITS-1 downto 0); |
|
I_ENBL : in std_logic_vector(I_WIDTH*ENBL_BITS-1 downto 0); |
|
I_DONE : in std_logic; |
|
I_FLUSH : in std_logic; |
|
I_VAL : in std_logic; |
|
I_RDY : out std_logic; |
|
O_DATA : out std_logic_vector(O_WIDTH*WORD_BITS-1 downto 0); |
|
O_ENBL : out std_logic_vector(O_WIDTH*ENBL_BITS-1 downto 0); |
|
O_DONE : out std_logic; |
|
O_FLUSH : out std_logic; |
|
O_VAL : out std_logic; |
|
O_RDY : in std_logic |
|
); |
|
end component; |
|
component REDUCER_TEST_MODEL is |
|
generic ( |
|
NAME : string; |
|
DELAY : time; |
|
WORD_BITS : integer; |
|
I_WIDTH : integer; |
|
O_WIDTH : integer; |
|
I_JUSTIFIED : integer; |
|
FLUSH_ENABLE: integer; |
|
AUTO_FINISH : integer |
|
); |
|
port( |
|
CLK : in std_logic; |
|
RST : out std_logic; |
|
CLR : out std_logic; |
|
START : out std_logic; |
|
OFFSET : out std_logic_vector(O_WIDTH-1 downto 0); |
|
DONE : out std_logic; |
|
FLUSH : out std_logic; |
|
I_DATA : out std_logic_vector(I_WIDTH*(WORD_BITS )-1 downto 0); |
|
I_ENBL : out std_logic_vector(I_WIDTH*(WORD_BITS/8)-1 downto 0); |
|
I_FLUSH : out std_logic; |
|
I_DONE : out std_logic; |
|
I_VAL : out std_logic; |
|
I_RDY : in std_logic := '0'; |
|
O_DATA : in std_logic_vector(O_WIDTH*(WORD_BITS )-1 downto 0) := (others => '0'); |
|
O_ENBL : in std_logic_vector(O_WIDTH*(WORD_BITS/8)-1 downto 0) := (others => '1'); |
|
O_FLUSH : in std_logic := '0'; |
|
O_DONE : in std_logic := '0'; |
|
O_VAL : in std_logic := '0'; |
|
O_RDY : out std_logic; |
|
BUSY : in std_logic; |
|
FINISH : out std_logic |
|
); |
|
end component; |
|
end COMPONENTS; |
