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`timescale 1ns / 1ps | |
module spi( | |
input clk_i, | |
input rst_i, | |
input miso_i, | |
output mosi_o, | |
output sck_o, | |
input start_i, | |
input [1:0]slave_i, | |
input[7:0] data_in_bi, | |
output[7:0] data_out_bo, | |
output busy_o, | |
output ready_o, | |
output ss1_o, | |
output ss2_o, | |
output ss3_o | |
); | |
reg [2:0] state_d, state_q; | |
reg [7:0] data_d, data_q; | |
reg [1:0] sck_d, sck_q; | |
reg mosi_d, mosi_q; | |
reg [2:0] ctr_d, ctr_q; | |
reg ready_d, ready_q; | |
reg [7:0] data_out_d, data_out_q; | |
wire ss1_q, ss2_q, ss3_q; | |
assign mosi_o = mosi_q; | |
assign sck_o = (~sck_q[1]) & (state_q == 2'd2); | |
assign busy_o = state_q != 2'd0; | |
assign data_out_bo = data_out_q; | |
assign ready_o = ready_q; | |
assign ss1_o = ~ss1_q; | |
assign ss2_o = ~ss2_q; | |
assign ss3_o = ~ss3_q; | |
demux1to4 demux ( | |
.Data_i(1'b1), | |
.sel(slave_i), | |
.Data_1_o(ss1_q), | |
.Data_2_o(ss2_q), | |
.Data_3_o(ss3_q) | |
); | |
always @(*) begin | |
sck_d = sck_q; | |
data_d = data_q; | |
mosi_d = mosi_q; | |
ctr_d = ctr_q; | |
ready_d = 1'b0; | |
data_out_d = data_out_q; | |
state_d = state_q; | |
case (state_q) | |
2'd0: begin // wait the start command | |
sck_d = 2'b0; | |
ctr_d = 3'b0; | |
$display("The value of slave_i is: %b", slave_i); | |
if (start_i == 1'b1) begin | |
data_d = data_in_bi; | |
state_d = 2'd1; | |
end | |
end | |
2'd1: begin // initialization of transmission | |
sck_d = sck_q + 1'b1; | |
if (sck_q == {1{1'b1}}) begin | |
sck_d = 1'b0; | |
state_d = 2'd2; | |
end | |
end | |
2'd2: begin // data transmission Master -> Slave, Slave -> Master | |
sck_d = sck_q + 1'b1; | |
if (sck_q == 2'b00) begin | |
mosi_d = data_q[7]; | |
end else if (sck_q == {1{1'b1}}) begin | |
data_d = {data_q[6:0], miso_i}; | |
end else if (sck_q =={2{1'b1}}) begin | |
ctr_d = ctr_q + 1'b1; | |
if (ctr_q == 3'b111) begin | |
state_d = 2'd0; | |
data_out_d = data_q; | |
ready_d = 1'b1; | |
end | |
end | |
end | |
endcase | |
end | |
always @(posedge clk_i) begin | |
if (rst_i) begin | |
ctr_q <= 3'b0; | |
data_q <= 8'b0; | |
sck_q <= 4'b0; | |
mosi_q <= 1'b0; | |
state_q <= 2'd0; | |
data_out_q <= 8'b0; | |
ready_q <= 1'b0; | |
end else begin | |
ctr_q <= ctr_d; | |
data_q <= data_d; | |
sck_q <= sck_d; | |
mosi_q <= mosi_d; | |
state_q <= state_d; | |
data_out_q <= data_out_d; | |
ready_q <= ready_d; | |
end | |
end | |
endmodule |
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