Created
July 13, 2020 02:38
-
-
Save andrewsclapp/4668b739f6014caef62fb689b0460a38 to your computer and use it in GitHub Desktop.
stm8l051 adc single read
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
\ ADC single scan mode 1 channel at a time | |
\res MCU: STM8L051 | |
\res export CLK_PCKENR2 ADC1_CR1 ADC1_CR2 ADC1_CR3 | |
\res export RI_ASCR1 RI_IOSR2 | |
\res export ADC1_SQR1 ADC1_SQR2 ADC1_SQR3 ADC1_SQR4 | |
\res export ADC1_DRH ADC1_DRL | |
\res export ADC1_SR | |
#require ]B! | |
#require ]B? | |
#require ]C! | |
#require WIPE | |
NVM | |
VARIABLE ADCVAR | |
\ adc initialisation | |
: adi ( --) | |
[ $81 CLK_PCKENR2 ]C! \ enable adc1 in clock gating reg | |
[ $82 RI_IOSR2 ]C! \ configure IOSR2 | |
[ $82 RI_ASCR1 ]C! \ configure ASCR1 | |
[ 2 ADC1_CR1 0 ]B! \ 0: Single conversion mode | |
[ 5 ADC1_CR1 0 ]B! \ set ADC resolution 12 bits | |
[ 6 ADC1_CR1 0 ]B! \ set ADC resolution 12 bits | |
[ 1 ADC1_CR1 0 ]B! \ ADON in ADC1_CR1 | |
[ 3 ADC1_CR2 0 ]B! \ software start enable - disable triggers | |
[ 4 ADC1_CR2 0 ]B! \ software start enable - disable triggers | |
[ 7 ADC1_CR2 ]C! \ 384 adc clock cycles for sampling | |
; | |
\ clear adc channels | |
: cadc | |
[ 0 ADC1_SQR4 ]C! | |
[ 0 ADC1_SQR3 ]C! | |
[ 0 ADC1_SQR2 ]C! | |
[ 0 ADC1_SQR1 ]C! | |
; | |
\ select adc channel | |
: sadc ( ch --) | |
cadc | |
DUP 8 < IF | |
1 ADC1_SQR4 ROT B! | |
ELSE | |
8 - DUP 8 < IF | |
1 ADC1_SQR3 ROT B! | |
ELSE | |
8 - DUP 8 < IF | |
1 ADC1_SQR2 ROT B! | |
ELSE | |
8 - 1 ADC1_SQR1 ROT B! | |
THEN | |
THEN | |
THEN | |
; | |
\ trigger adc and write to ADCVAR | |
: tadc ( --) | |
\ trigger adc | |
[ 1 ADC1_CR1 1 ]B! | |
begin [ ADC1_SR 0 ]B? 0 = until | |
\ write output from adc_dr to variable | |
\ first one's junk | |
ADC1_DRH @ DROP | |
ADC1_DRH @ ADCVAR ! | |
; | |
: adcoff | |
[ 0 ADC1_CR1 0 ]B! \ Disable | |
; | |
: scanv | |
adi \ initialize | |
4 sadc \ clear all channels - set channel | |
tadc \ trigger the adc | |
ADC1_DRH @ DROP ADC1_DRH @ ADCVAR ! | |
adcoff | |
; | |
: scana | |
adi \ initialize | |
22 sadc \ clear all channels - set channel | |
tadc \ trigger the adc | |
ADC1_DRH @ DROP ADC1_DRH @ ADCVAR ! | |
adcoff | |
; | |
WIPE | |
RAM | |
\\ example | |
scanv ADCVAR @ . |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment