Created
June 15, 2021 15:15
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SpiXdr Register map
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- peripheral: | |
groupName: SPIXDR | |
description: Management Data Input Output | |
registers: | |
- register: | |
- name: DATA | |
description: Data register | |
addressOffset: 0x00 | |
fields: | |
- field: | |
- name: DATA | |
resetValue: 0 | |
msb: 7 | |
lsb: 0 | |
- field: | |
- name: CMD_WRITE | |
access: write-only | |
resetValue: 0 | |
msb: 8 | |
lsb: 8 | |
- field: | |
- name: CMD_READ | |
access: write-only | |
resetValue: 0 | |
msb: 9 | |
lsb: 9 | |
- field: | |
- name: CMD_CS | |
access: write-only | |
resetValue: 0 | |
msb: 11 | |
lsb: 11 | |
- field: | |
- name: RSP_VALID | |
resetValue: 0 | |
access: read-only | |
msb: 31 | |
lsb: 31 | |
- register: | |
- name: BUFFER | |
description: Buffer status register | |
addressOffset: 0x04 | |
fields: | |
- field: | |
- name: CMD_AVAILABILITY | |
access: read-only | |
msb: 15 | |
lsb: 0 | |
- field: | |
- name: RSP_OCCUPANCY | |
access: read-only | |
msb: 31 | |
lsb: 16 | |
- register: | |
- name: CONFIG | |
description: Configuration register | |
addressOffset: 0x08 | |
fields: | |
- field: | |
- name: CPOL | |
access: write-only | |
msb: 0 | |
lsb: 0 | |
- field: | |
- name: CPHA | |
access: write-only | |
msb: 1 | |
lsb: 1 | |
- field: | |
- name: MODE | |
access: write-only | |
msb: 4 | |
lsb: 4 | |
- register: | |
- name: INTERRUPT | |
description: interrupt control & status register. the peripheral IRQ line is CMD_INT || RSP_INT | |
addressOffset: 0x0C | |
fields: | |
- field: | |
- name: CMD_INT_EN | |
msb: 0 | |
lsb: 0 | |
- field: | |
- name: RSP_INT_EN | |
msb: 1 | |
lsb: 1 | |
- field: | |
- name: CMD_INT | |
description: true when cmd buffer valid is low (buffer is empty?) & CMD_INT_EN == 1 | |
access: read-only | |
msb: 8 | |
lsb: 8 | |
- field: | |
- name: RSP_INT | |
description: true when rsp buffer is valid and RSP_INT_EN == true | |
access: read-only | |
msb: 9 | |
lsb: 9 | |
- field: | |
- name: CMD_VALID | |
access: read-only | |
msb: 16 | |
lsb: 16 | |
- register: | |
- name: CLK_DIV | |
addressOffset: 0x20 | |
description: 12 bit timer for clock divider | |
access: write-only | |
- register: | |
- name: CS_SETUP | |
description: 12 bit timer for cs setup | |
addressOffset: 0x24 | |
access: write-only | |
- register: | |
- name: CS_HOLD | |
addressOffset: 0x28 | |
description: 12 bit timer for cs | |
access: write-only | |
- register: | |
- name: CS_DISABLE | |
addressOffset: 0x2C | |
description: 12 bit timer for cs disable | |
access: write-only | |
- register: | |
- name: CS_ACTIVE_HIGH | |
addressOffset: 0x30 | |
description: bitfield of active high SS | |
access: write-only |
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