As the tagline says, if you're trying to use Emacs's built-n project-management package, project.el, to add a git version-controlled project that git deems untrustworthy and then do a project-find-{files,dir} on it, it will currently crash, because the output of the git ls-files outputs a bunch of errors to stderr and nothing to stdout, and it doesn't expect to have an empty list of files and directories. To resolve this, I've created a nice snipped of code that will detect, when you add a project, whether git deems it unsafe (git ls-files returns code 128 to mean that) and ask you whether you want to add it to your list of safe directories:

(advice-add 'project-remember-project
                :before (lambda (pr &optional something)
                            (when (and (eq 'Git (cadr pr))
                                       (let ((default-directory (caddr pr)))
                                           (= (shell-command "git ls-files") 128)))
                                (when (y-or-n-

A finite state machine is a way of representing the logic of a system that has some kind of internal state. It defines a set of distinct states which a system can be in, as well as which states can transition to which other states and which inputs make the state change from one to another. For example, a simple finite state machine might represent a train with three states: Boarding, InTransit, and Disembarking. The train starts out in the Boarding state, and from the Boarding state can only go to InTransit (since people don't get on a train just to get off again). Once the train is InTransit, it can only either stay that way, or go to Disembarking. Only when it is in the Disembarking state can it go to the Boarding state again, since you can't board a train before it's empty. The transitions between these states would happen according to some input to the machine from somewhere else in your program --- maybe a "next" button, for instance.

There are two kinds of finite state machines: Mealy machines, and Moo

There are two basic ways that you can write a Verilog program:

1. Structural Verilog: this is where you specify the logic gates and connections between them of your circuit directly, as if you were doing a textual version of drawing logic gate circuits. This is very low level and nitty-gritty. Here's an example of what that looks like: