First, if you are on Windows and find some of these commands are not found in the EDS Command Shell, then you may need to add your Quartus path. I did this by editing the env.sh file and adding the following line:
export QUARTUS_ROOTDIR_OVERRIDE="/cygdrive/c/intelFPGA_lite/16.1/quartus"
From here, someone could easily make a script for their project that allows for easily making and building all the necessary items.
For editing Qsys run the following command. Change soc_system.qsys to your Qsys file or leave blank if you do not have one.
qsys-edit soc_system.qsys
I recommend using the GUI to do this because it is simply easier to click and connect things to/from the bus. It is a nice convenience.
If you make changes to a custom IP and it is not showing in qsys, then I suggest pressing F5 in the GUI to refresh the system. It will reload the TCL files. Also, you can generate from command line with the following command or just press generate in the GUI.
To generate from commandline, run:
qsys-generate --block-symbol-file --synthesis=VERILOG soc_system.qsys
You should only need to regenerate qsys if you made changes to the .qsys file OR if you made changes to an IP that is made in qsys. When you generate the qsys project, it copies all of the Verilog files to a new directory (soc_system in this case), so if you made changes to the custom IP, they won't copy over to the generated directory. If you are wanting to do some quick testing, then you can find the copy of your module in generated directory and make changes. However, note to copy those over when you are finished so that they are not lost when you generate again.
The process for generating the project is Map -> Fitter -> Assembly -> Timing Analysis
When you generate the qsys project, there are a few TCL scripts that need to be run to setup the critical timing paths for the HPS pins. You must run mapping on the project, run the TCL scripts, and then you can finish running the other parts of the compilation process. This only needs to be done ONCE per project. Afterwards, you can just run the steps above.
You only need to run the three commands the FIRST time compiling the project:
quartus_map <PROJECT_NAME, ex. FFTRAMSoC in my case>
quartus_sh -t soc_system/synthesis/submodules/hps_sdram_p0_parameters.tcl <PROJECT_NAME>
quartus_sh -t soc_system/synthesis/submodules/hps_sdram_p0_pin_assignments.tcl <PROJECT_NAME>
Afterwards, you can build it with:
quartus_sh --flow compile FFTRAMSoC
The final step is to convert the generated SOF file to RBF to put on the SD card. This can be done via the command-line and a COF file that describes how to convert the file. You only need to create the COF once and then you can use that to generate the RBF file each time.
There are two ways to create the COF. First, you can open an existing COF from the Internet and update it to suit your needs. The second way is to open Quartus Prime, go to File->Convert Programming Files, setup how you want to convert the files, and then click "Save Conversion Setup" to save a COF.
To compile the SOF into a RBF using the COF, run this command:
quartus_cpf -c <COF_FILE_HERE>.cof
**Note: **In my project, I put the COF file in the output_files directory.
Begin by configuring the preloader via a GUI interface. Run:
bsp-editor
Note: If you have already generated the preloader before, change into software/spl_bsp and then run bsp-editor. This will open the existing project.
Do the stuff you need in the editor.
To generate the preloader from the command-line, run the command below. You can also generate the project from within the bsp-editor GUI by clicking "Generate" at the bottom.
bsp-generate-files --settings settings.bsp --bsp-dir .
Note: Make sure you are in the software/spl_bsp directory.
Run the following to make the preloader and U-boot:
make && make uboot
After generating the preloader and U-boot, it is probably a good idea to generate the device tree too. This should be done at the top-level of the project.
sopc2dts --input soc_system.sopcinfo --output socfpga.dts --type dts --board soc_system_board_info.xml --board hps_common_board_info.xml --bridge-removal all --clocks
dtc -I dts -O dtb -o socfpga.dtb socfpga.dts
Generating the preloader and U-boot is not ALWAYS necessary. If you only updated Verilog or FPGA-related stuff WITHOUT changing anything on the HPS side, then the existing preloader and U-boot should be fine. For example, if you just changed some code in your custom IP module in Verilog, then the existing preloader and U-boot should be fine. However, if you change the bus-width for the lightweight HPS-to-FPGA bus, then that would require regenerating the preloader and U-boot
If the structure of the qsys system or if this is the first time generating it, then you will need to regenerate the header file that contains address mapping for each qsys component.
In my case, I put this in /software_programs directory. Here is the command you need to run. You may need to change the path to the SOPCINFO file depending where you store it. The output is hps_0.h that you include in your programs.
sopc-create-header-files "../soc_system.sopcinfo" --single hps_0.h --module hps_0
Then you just need to make your programs if you haven't made them yet. Just have a makefile for them and make them.
This is specific to Windows and Cygwin. It will need to be adapted for Linux.
Copy all of our files. Assuming you are at the top-level of the directory, then you can run:
alt-boot-disk-util.exe -p software/spl_bsp/preloader-mkpimage.bin -a write -d <SD_DRIVE_LETTER, ex. g>
cp software/spl_bsp/uboot-socfpga/u-boot.img /cygdrive/<SD_DRIVE_LETTER>/
cp soc_system.rbf /cygdrive/<SD_DRIVE_LETTER>/
cp socfpga.dtb /cygdrive/<SD_DRIVE_LETTER>/
sync
Don't forget to copy your program on SD card too.
Remove the card and place it in your DE10 Nano. It should be good.