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September 27, 2021 09:15
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Welcome to minicom 2.8 | |
OPTIONS: | |
Port /dev/ttyUSB0, 17:13:45 | |
Press CTRL-A Z for help on special keys | |
=================================================================== | |
MT7621 stage1 code 10:33:55 (ASIC) | |
CPU=500000000 HZ BUS=166666666 HZ | |
================================================================== | |
Change MPLL source from XTAL to CR... | |
do MEMPLL setting.. | |
MEMPLL Config : 0x11100000 | |
3PLL mode + External loopback | |
=== XTAL-40Mhz === DDR-1200Mhz === | |
PLL4 FB_DL: 0xd, 1/0 = 702/322 35000000 | |
PLL2 FB_DL: 0x10, 1/0 = 587/437 41000000 | |
PLL3 FB_DL: 0x16, 1/0 = 717/307 59000000 | |
do DDR setting..[01F40000] | |
Apply DDR3 Setting...(use customer AC) | |
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 | |
-------------------------------------------------------------------------------- | |
0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
0007:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
0008:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
0009:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 | |
000E:| 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 | |
000F:| 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 | |
0010:| 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 | |
0011:| 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
0012:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
0013:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
rank 0 coarse = 15 | |
rank 0 fine = 64 | |
B:| 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 | |
opt_dle value:9 | |
DRAMC_R0DELDLY[018]=00001E1F | |
================================================================== | |
RX DQS perbit delay software calibration | |
================================================================== | |
1.0-15 bit dq delay value | |
================================================================== | |
bit| 0 1 2 3 4 5 6 7 8 9 | |
-------------------------------------- | |
0 | 9 9 9 11 9 9 10 8 8 9 | |
10 | 9 11 10 11 10 11 | |
-------------------------------------- | |
================================================================== | |
2.dqs window | |
x=pass dqs delay value (min~max)center | |
y=0-7bit DQ of every group | |
input delay:DQS0 =31 DQS1 = 30 | |
================================================================== | |
bit DQS0 bit DQS1 | |
0 (1~60)30 8 (1~58)29 | |
1 (1~59)30 9 (1~59)30 | |
2 (1~57)29 10 (1~59)30 | |
3 (1~61)31 11 (1~58)29 | |
4 (1~60)30 12 (1~60)30 | |
5 (1~61)31 13 (1~56)28 | |
6 (1~60)30 14 (1~59)30 | |
7 (1~62)31 15 (1~58)29 | |
================================================================== | |
3.dq delay value last | |
================================================================== | |
bit| 0 1 2 3 4 5 6 7 8 9 | |
-------------------------------------- | |
0 | 10 10 11 11 10 9 11 8 9 9 | |
10 | 9 12 10 13 10 12 | |
================================================================== | |
================================================================== | |
TX perbyte calibration | |
================================================================== | |
DQS loop = 15, cmp_err_1 = ffff0000 | |
dqs_perbyte_dly.last_dqsdly_pass[0]=15, finish count=1 | |
dqs_perbyte_dly.last_dqsdly_pass[1]=15, finish count=2 | |
DQ loop=15, cmp_err_1 = ffff0080 | |
dqs_perbyte_dly.last_dqdly_pass[1]=15, finish count=1 | |
DQ loop=14, cmp_err_1 = ffff0000 | |
dqs_perbyte_dly.last_dqdly_pass[0]=14, finish count=2 | |
byte:0, (DQS,DQ)=(8,8) | |
byte:1, (DQS,DQ)=(8,8) | |
20,data:88 | |
[EMI] DRAMC calibration passed | |
=================================================================== | |
MT7621 stage1 code done | |
CPU=500000000 HZ BUS=166666666 HZ | |
=================================================================== | |
U-Boot 1.1.3 (Apr 24 2017 - 10:34:37) | |
Board: Ralink APSoC DRAM: 256 MB | |
relocate_code Pointer at: 8ffb8000 | |
Config XHCI 40M PLL | |
flash manufacture id: 68, device id 40 18 | |
Warning: un-recognized chip ID, please update bootloader! | |
============================================ | |
Ralink UBoot Version: 5.0.0.0 | |
-------------------------------------------- | |
ASIC MT7621A DualCore (MAC to MT7530 Mode) | |
DRAM_CONF_FROM: Auto-Detection | |
DRAM_TYPE: DDR3 | |
DRAM bus: 16 bit | |
Xtal Mode=3 OCP Ratio=1/3 | |
Flash component: SPI Flash | |
Date:Apr 24 2017 Time:10:34:37 | |
============================================ | |
icache: sets:256, ways:4, linesz:32 ,total:32768 | |
dcache: sets:256, ways:4, linesz:32 ,total:32768 | |
##### The CPU freq = 880 MHZ #### | |
estimate memory size =256 Mbytes | |
#Reset_MT7530 | |
set LAN/WAN LLLLW | |
Please choose the operation: | |
1: Load system code to SDRAM via TFTP. | |
2: Load system code then write to Flash via TFTP. | |
3: Boot system code via Flash (default). | |
4: Entr boot command line interface. | |
7: Load Boot Loader code then write to Flash via Serial. | |
9: Load Boot Loader code then write to Flash via TFTP. | |
default: 3 |
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